PCB Case Studies & Practical Application 5

Question 1

A designer reviews a schematic and finds a 10k pull-up resistor on an I2C SDA line that is 2 meters long (using cable extension). The bus runs at 400 kHz (Fast Mode). What is the likely problem?

Accepted Answer

The long cable capacitance combined with 10k pull-up creates RC time constant that slows rising edges below Fast Mode spec

Answer

I2C Fast Mode requires rise times under 300ns; long cables add 100-200pF/meter of capacitance, and 10k × 200pF = 2µs RC time constant, far exceeding the 300ns limit.

Question 2

A PCB design for a Class II medical device (IEC 60601-1) requires 8mm creepage between the mains input and patient-contact circuits. The designer has 5mm on the current layout. What are the options?

Accepted Answer

Increase board size, add slots/cutouts between mains and patient circuits, or use approved reinforced insulation barriers

Answer

IEC 60601-1 creepage requirements cannot be met by coating alone at mains voltages; physical solutions include board slots, increased spacing, or approved double/reinforced insulation components.

Question 3

During PCB panelization design, V-score breakaway tabs are used. After depaneling, boards show micro-cracks near edge components placed 50 mils from the V-score line. What is the correct design fix?

Accepted Answer

Move components at least 100-125 mils from V-score lines, or switch to routed tabs for vibration-sensitive areas

Answer

V-score depaneling transmits mechanical stress several hundred mils into the board; IPC recommends keeping components 100-125 mils minimum from V-score lines to prevent cracking.

Question 4

A PCB with an on-board switching regulator shows excessive output ripple at 2x the switching frequency. The output capacitors and layout appear correct. What is the likely cause?

Accepted Answer

Second harmonic ripple indicates subharmonic oscillation often caused by insufficient slope compensation in peak current-mode control

Answer

Ripple at 2x the switching frequency in current-mode control indicates subharmonic instability, which occurs when the inductor current up-slope exceeds half the down-slope without adequate slope compensation.

Question 5

A network switch PCB uses 10Gb/s SerDes lanes routed as 100-ohm differential pairs. The SI simulation shows excess insertion loss at 5 GHz. The traces are 12 inches long on a standard FR4 laminate. What is the recommended solution?

Accepted Answer

Switch to a low-loss laminate material (e.g., Megtron 6 or Rogers 4350B) to reduce dielectric loss at high frequencies

Answer

Standard FR4 has high dielectric loss tangent (Df ≈ 0.02) that causes significant signal attenuation at 5GHz over 12 inches; low-loss laminates with Df < 0.005 are necessary for 10Gb/s+ SerDes.

PCB - Design Practice Test

PCB - Design Practice Test

PCB Case Studies & Practical Application 5