PCB Case Studies & Practical Application 5 — Questions and Answers
Question 1: A designer reviews a schematic and finds a 10k pull-up resistor on an I2C SDA line that is 2 meters long (using cable extension). The bus runs at 400 kHz (Fast Mode). What is the likely problem?
- The resistor value is too high, causing excessive current draw
- The long cable capacitance combined with 10k pull-up creates RC time constant that slows rising edges below Fast Mode spec (Correct answer)
- Pull-up voltage must match the cable impedance
- 10k is the correct value for Fast Mode I2C
Correct answer: The long cable capacitance combined with 10k pull-up creates RC time constant that slows rising edges below Fast Mode spec
I2C Fast Mode requires rise times under 300ns; long cables add 100-200pF/meter of capacitance, and 10k × 200pF = 2µs RC time constant, far exceeding the 300ns limit.
Question 2: A PCB design for a Class II medical device (IEC 60601-1) requires 8mm creepage between the mains input and patient-contact circuits. The designer has 5mm on the current layout. What are the options?
- Add conformal coating to reduce required creepage distance
- Increase board size, add slots/cutouts between mains and patient circuits, or use approved reinforced insulation barriers (Correct answer)
- Use higher voltage rated components to compensate
- Move to a multi-layer board to route the traces on inner layers
Correct answer: Increase board size, add slots/cutouts between mains and patient circuits, or use approved reinforced insulation barriers
IEC 60601-1 creepage requirements cannot be met by coating alone at mains voltages; physical solutions include board slots, increased spacing, or approved double/reinforced insulation components.
Question 3: During PCB panelization design, V-score breakaway tabs are used. After depaneling, boards show micro-cracks near edge components placed 50 mils from the V-score line. What is the correct design fix?
- Use thicker board material to reduce cracking
- Move components at least 100-125 mils from V-score lines, or switch to routed tabs for vibration-sensitive areas (Correct answer)
- Apply underfill to all edge components
- Increase V-score depth to make depaneling easier
Correct answer: Move components at least 100-125 mils from V-score lines, or switch to routed tabs for vibration-sensitive areas
V-score depaneling transmits mechanical stress several hundred mils into the board; IPC recommends keeping components 100-125 mils minimum from V-score lines to prevent cracking.
Question 4: A PCB with an on-board switching regulator shows excessive output ripple at 2x the switching frequency. The output capacitors and layout appear correct. What is the likely cause?
- The switching frequency is set too high
- Second harmonic ripple indicates subharmonic oscillation often caused by insufficient slope compensation in peak current-mode control (Correct answer)
- Output capacitor ESR is too low
- The feedback resistor divider values are incorrect
Correct answer: Second harmonic ripple indicates subharmonic oscillation often caused by insufficient slope compensation in peak current-mode control
Ripple at 2x the switching frequency in current-mode control indicates subharmonic instability, which occurs when the inductor current up-slope exceeds half the down-slope without adequate slope compensation.
Question 5: A network switch PCB uses 10Gb/s SerDes lanes routed as 100-ohm differential pairs. The SI simulation shows excess insertion loss at 5 GHz. The traces are 12 inches long on a standard FR4 laminate. What is the recommended solution?
- Increase trace width to reduce resistance
- Switch to a low-loss laminate material (e.g., Megtron 6 or Rogers 4350B) to reduce dielectric loss at high frequencies (Correct answer)
- Add more ground vias along the trace route
- Reduce the number of vias in the signal path
Correct answer: Switch to a low-loss laminate material (e.g., Megtron 6 or Rogers 4350B) to reduce dielectric loss at high frequencies
Standard FR4 has high dielectric loss tangent (Df ≈ 0.02) that causes significant signal attenuation at 5GHz over 12 inches; low-loss laminates with Df < 0.005 are necessary for 10Gb/s+ SerDes.
Question 6: A PCB assembly uses lead-free solder (SAC305) but a legacy component with SnPb finish is accidentally included. What reliability concern does this create?
- Higher melting point of SnPb will prevent the joint from forming
- Mixed metallurgy can create Bi-containing intermetallics if Bi is present, or cause joint reliability issues from inconsistent microstructure (Correct answer)
- Lead contamination will cause immediate electrical failure
- The joint will have excessive voiding due to flux incompatibility
Correct answer: Mixed metallurgy can create Bi-containing intermetallics if Bi is present, or cause joint reliability issues from inconsistent microstructure
Mixing SAC305 lead-free solder with SnPb-finished components creates inconsistent joint microstructure; while often acceptable in practice, it can reduce fatigue life and creates regulatory non-compliance for RoHS products.
Question 7: A PCB designer is adding test points to a dense board for ICT access. The test engineer requires 100-mil grid placement. The designer proposes using component pads as test points instead. What is the risk?
- Component pads are not electrically accessible for ICT probes
- Probing component pads can cause mechanical damage to solder joints and may not align to the 100-mil ICT grid (Correct answer)
- ICT cannot measure component values through their pads
- Component pad materials are incompatible with ICT probes
Correct answer: Probing component pads can cause mechanical damage to solder joints and may not align to the 100-mil ICT grid
ICT bed-of-nails fixtures require 100-mil grid alignment for probe tooling; component pads are rarely on-grid, and probing them risks cracking solder joints or lifting pads.
PCB Case Studies & Practical Application 5
A designer reviews a schematic and finds a 10k pull-up resistor on an I2C SDA line that is 2 meters long (using cable extension).
The bus runs at 400 kHz (Fast Mode).
What is the likely problem?