PCB Case Studies & Practical Application 3

Question 1

A four-layer board stackup is: Top (signal), L2 (GND), L3 (PWR), Bottom (signal). A designer wants to route high-speed signals on the Bottom layer. What is the concern?

Accepted Answer

High-speed signals on Bottom reference the PWR plane, not GND, causing impedance issues

Answer

The Bottom layer is adjacent to the PWR plane (L3), not GND (L2), so high-speed signals there have a noisy power reference rather than a clean ground reference, degrading signal integrity.

Question 2

A prototype PCB has multiple net shorts detected after assembly. X-ray inspection shows solder bridging under BGA packages. What design change prevents this in the next revision?

Accepted Answer

Ensure correct solder mask defined (SMD) vs non-solder mask defined (NSMD) pad selection and verify paste aperture reduction

Answer

BGA bridging is often caused by incorrect pad definition (SMD vs NSMD) or paste apertures that are too large; NSMD pads with appropriate aperture reduction per IPC-7525 reduces bridging risk.

Question 3

A designer needs to place a 0.1µF decoupling capacitor for a 3.3V IC. Where should it be placed relative to the IC power pin?

Accepted Answer

As close as possible to the IC power pin, with the via to ground closer to the capacitor than to the IC

Answer

Placing the decoupling capacitor directly at the IC power pin minimizes parasitic inductance in the supply path; the ground via should be near the capacitor to minimize the ground return loop.

Question 4

During DFM review, the fabricator flags 6-mil traces with 6-mil spacing in a dense region. The board is specified as IPC Class 2. What is the issue?

Accepted Answer

6/6 mil rules are within standard Class 2 capability; no issue

Answer

Standard PCB fabricators routinely support 6-mil trace/space for IPC Class 2 boards; 6/6 mil is well within typical manufacturing capability and should not cause a DFM flag.

Question 5

A rigid-flex PCB design for a wearable device fails flex cycling tests at 50,000 cycles. The traces in the flex region are 3 mils wide oriented perpendicular to the bend axis. What redesign is needed?

Accepted Answer

Increase trace width and orient traces parallel to the bend axis

Answer

Traces in flex regions should be routed parallel to the bend axis to minimize strain; perpendicular traces experience maximum bending stress and fail sooner; wider traces also reduce stress concentration.

PCB - Design Practice Test

PCB - Design Practice Test

PCB Case Studies & Practical Application 3