PCB Case Studies & Practical Application 3 — Questions and Answers
Question 1: A four-layer board stackup is: Top (signal), L2 (GND), L3 (PWR), Bottom (signal). A designer wants to route high-speed signals on the Bottom layer. What is the concern?
- Bottom layer copper is thinner than Top layer
- High-speed signals on Bottom reference the PWR plane, not GND, causing impedance issues (Correct answer)
- Silkscreen on Bottom interferes with high-speed signals
- Bottom layer vias have higher inductance
Correct answer: High-speed signals on Bottom reference the PWR plane, not GND, causing impedance issues
The Bottom layer is adjacent to the PWR plane (L3), not GND (L2), so high-speed signals there have a noisy power reference rather than a clean ground reference, degrading signal integrity.
Question 2: A prototype PCB has multiple net shorts detected after assembly. X-ray inspection shows solder bridging under BGA packages. What design change prevents this in the next revision?
- Increase BGA pad size to maximum
- Ensure correct solder mask defined (SMD) vs non-solder mask defined (NSMD) pad selection and verify paste aperture reduction (Correct answer)
- Remove all solder mask between BGA pads
- Use larger BGA ball pitch
Correct answer: Ensure correct solder mask defined (SMD) vs non-solder mask defined (NSMD) pad selection and verify paste aperture reduction
BGA bridging is often caused by incorrect pad definition (SMD vs NSMD) or paste apertures that are too large; NSMD pads with appropriate aperture reduction per IPC-7525 reduces bridging risk.
Question 3: A designer needs to place a 0.1µF decoupling capacitor for a 3.3V IC. Where should it be placed relative to the IC power pin?
- Anywhere on the board connected to the same net
- As close as possible to the IC power pin, with the via to ground closer to the capacitor than to the IC (Correct answer)
- Between the bulk capacitor and the IC
- On the opposite side of the board from the IC
Correct answer: As close as possible to the IC power pin, with the via to ground closer to the capacitor than to the IC
Placing the decoupling capacitor directly at the IC power pin minimizes parasitic inductance in the supply path; the ground via should be near the capacitor to minimize the ground return loop.
Question 4: During DFM review, the fabricator flags 6-mil traces with 6-mil spacing in a dense region. The board is specified as IPC Class 2. What is the issue?
- 6/6 mil rules are within standard Class 2 capability; no issue (Correct answer)
- Most standard PCB fabs require 4-mil minimum for Class 2 boards
- Class 2 requires 10-mil minimum spacing
- The issue is the trace width, not the spacing
Correct answer: 6/6 mil rules are within standard Class 2 capability; no issue
Standard PCB fabricators routinely support 6-mil trace/space for IPC Class 2 boards; 6/6 mil is well within typical manufacturing capability and should not cause a DFM flag.
Question 5: A rigid-flex PCB design for a wearable device fails flex cycling tests at 50,000 cycles. The traces in the flex region are 3 mils wide oriented perpendicular to the bend axis. What redesign is needed?
- Increase trace width and orient traces parallel to the bend axis (Correct answer)
- Add stiffener material to the flex region
- Reduce the number of traces in the flex zone
- Switch to polyimide coverlay with higher glass transition temperature
Correct answer: Increase trace width and orient traces parallel to the bend axis
Traces in flex regions should be routed parallel to the bend axis to minimize strain; perpendicular traces experience maximum bending stress and fail sooner; wider traces also reduce stress concentration.
Question 6: An IoT device PCB must pass FCC Part 15 unintentional radiator testing. The crystal oscillator is located 2 inches from the microcontroller. What is the primary concern?
- Crystal may not start up at 2-inch distance
- Long traces between crystal and MCU act as antennas, radiating at the fundamental and harmonic frequencies (Correct answer)
- Impedance mismatch between crystal and MCU
- The crystal load capacitors may be the wrong value at that distance
Correct answer: Long traces between crystal and MCU act as antennas, radiating at the fundamental and harmonic frequencies
Crystal oscillator traces should be as short as possible; long traces radiate at the oscillator frequency and its harmonics, making FCC compliance much harder to achieve.
Question 7: A PCB designer is reviewing a schematic where a MOSFET gate driver output connects to the gate with a 100-ohm resistor. The designer wants to speed up switching. What is the tradeoff of reducing this resistor to 10 ohms?
- Lower resistance increases gate voltage, improving threshold margin
- Faster switching reduces losses but increases dV/dt and dI/dt, worsening EMI and potentially causing ringing (Correct answer)
- Lower gate resistance reduces power dissipation in the driver
- Faster switching reduces shoot-through current in the MOSFET
Correct answer: Faster switching reduces losses but increases dV/dt and dI/dt, worsening EMI and potentially causing ringing
Reducing gate resistance speeds switching and reduces switching losses, but the faster dV/dt and dI/dt edges cause more severe ringing and EMI due to parasitic inductances in the gate loop.
PCB Case Studies & Practical Application 3
A four-layer board stackup is: Top (signal), L2 (GND), L3 (PWR), Bottom (signal).
A designer wants to route high-speed signals on the Bottom layer.
What is the concern?