GROL Digital Logic and Microcomputers 3

Question 1

What is the primary difference between a D flip-flop and a D latch?

Accepted Answer

A flip-flop is edge-triggered; a latch is level-sensitive

Answer

A D flip-flop captures data on a clock edge, while a D latch is transparent whenever the enable signal is active (level-sensitive).

Question 2

A 4-bit binary ripple counter is clocked at 16 kHz. What is the output frequency at the most significant bit (Q3)?

Accepted Answer

1 kHz

Answer

Each flip-flop in a ripple counter divides by 2, so a 4-stage counter divides by 16: 16 kHz ÷ 16 = 1 kHz at Q3.

Question 3

Which type of shift register transfers data serially in and serially out?

Accepted Answer

SISO

Answer

SISO (Serial-In, Serial-Out) receives and transmits data one bit at a time.

Question 4

In a JK flip-flop, what happens when both J and K inputs are logic 1 and a clock pulse arrives?

Accepted Answer

Output toggles

Answer

With J=K=1, the JK flip-flop toggles its output on each clock pulse, solving the race condition of the SR flip-flop.

Question 5

A 3-bit synchronous counter counts from 000 to 111 and repeats. How many clock pulses are needed to complete one full cycle?

Accepted Answer

8

Answer

A 3-bit counter has 2³ = 8 unique states (000 through 111), requiring 8 clock pulses for one complete cycle.

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