GROL Digital Logic and Microcomputers 3 — Questions and Answers
Question 1: What is the primary difference between a D flip-flop and a D latch?
- A flip-flop is edge-triggered; a latch is level-sensitive (Correct answer)
- A latch is edge-triggered; a flip-flop is level-sensitive
- They operate identically
- A flip-flop has no clock input
Correct answer: A flip-flop is edge-triggered; a latch is level-sensitive
A D flip-flop captures data on a clock edge, while a D latch is transparent whenever the enable signal is active (level-sensitive).
Question 2: A 4-bit binary ripple counter is clocked at 16 kHz. What is the output frequency at the most significant bit (Q3)?
- 16 kHz
- 8 kHz
- 2 kHz
- 1 kHz (Correct answer)
Correct answer: 1 kHz
Each flip-flop in a ripple counter divides by 2, so a 4-stage counter divides by 16: 16 kHz ÷ 16 = 1 kHz at Q3.
Question 3: Which type of shift register transfers data serially in and serially out?
- SIPO
- PISO
- SISO (Correct answer)
- PIPO
Correct answer: SISO
SISO (Serial-In, Serial-Out) receives and transmits data one bit at a time.
Question 4: In a JK flip-flop, what happens when both J and K inputs are logic 1 and a clock pulse arrives?
- Output is set to 1
- Output is reset to 0
- Output is unchanged
- Output toggles (Correct answer)
Correct answer: Output toggles
With J=K=1, the JK flip-flop toggles its output on each clock pulse, solving the race condition of the SR flip-flop.
Question 5: A 3-bit synchronous counter counts from 000 to 111 and repeats. How many clock pulses are needed to complete one full cycle?
- 3
- 6
- 7
- 8 (Correct answer)
Correct answer: 8
A 3-bit counter has 2³ = 8 unique states (000 through 111), requiring 8 clock pulses for one complete cycle.
Question 6: What is the main advantage of a synchronous counter over an asynchronous (ripple) counter?
- Uses fewer flip-flops
- All flip-flops are clocked simultaneously, eliminating propagation delays (Correct answer)
- Counts in both directions
- Requires no clock signal
Correct answer: All flip-flops are clocked simultaneously, eliminating propagation delays
Synchronous counters clock all flip-flops at the same time, preventing cumulative propagation delay and glitches.
Question 7: Which register operation moves all bits one position toward the most significant bit, filling the LSB with zero?
- Logical right shift
- Logical left shift (Correct answer)
- Arithmetic right shift
- Rotate right
Correct answer: Logical left shift
A logical left shift moves all bits toward the MSB by one position and inserts a 0 at the LSB, which is equivalent to multiplying by 2.
GROL Digital Logic and Microcomputers 3
What is the primary difference between a D flip-flop and a D latch?