ALU 101 Adder Circuits and Addition Logic 2

Question 1

What key technique does a carry lookahead adder (CLA) use to improve speed?

Accepted Answer

Computes all carry bits in parallel using generate and propagate signals

Answer

A carry lookahead adder precomputes all carry bits simultaneously using generate (G) and propagate (P) signals, eliminating the ripple delay.

Question 2

In carry lookahead logic, what does the 'generate' signal (G = A·B) indicate?

Accepted Answer

The stage will always produce a carry-out regardless of the carry-in

Answer

G = A·B means both inputs are 1, so a carry is generated at that stage no matter what value the carry-in holds.

Question 3

In carry lookahead logic, what does the 'propagate' signal (P = A XOR B) indicate?

Accepted Answer

The stage will pass an incoming carry-in to its carry-out

Answer

P = A⊕B means exactly one input is 1, so if carry-in is 1, the stage will forward it as carry-out.

Question 4

For a 1-bit stage with inputs A=1 and B=1, what are the values of the generate (G) and propagate (P) signals?

Accepted Answer

G=1, P=0

Answer

When A=1 and B=1, G = A·B = 1 and P = A⊕B = 0, so the stage generates a carry but does not propagate one.

Question 5

What is the correct carry-in value for the least significant bit (LSB) stage in a standard unsigned multi-bit addition?

Accepted Answer

0

Answer

There is no carry coming into the LSB position from a lower stage, so the carry-in is defined as 0 for unsigned addition.

ALU 101 - Arithmetic Logic Unit 101 Exam Practice Test