CID CID Layout & Routing Techniques 2

Question 1

What is 'daisy-chain' topology in PCB routing for buses, and what is its primary advantage?

Accepted Answer

Routing a single trace that passes through each load sequentially; advantage is minimal stub lengths for source-terminated buses

Answer

Daisy-chain topology routes one continuous trace through each device in sequence, minimizing stub lengths and supporting source termination for controlled-impedance buses.

Question 2

What does 'length matching' mean for a memory bus, and to what tolerance is it typically specified?

Accepted Answer

Address, data, and clock traces are matched in length within a specified tolerance (e.g., ±5 mils) to control propagation delay skew

Answer

Length matching controls propagation delay skew across bus signals so that all bits of a data word arrive at the receiver within the timing window, with tolerances typically specified in mils by the chipset reference design.

Question 3

What is a 'serpentine' (meander) trace used for in PCB layout?

Accepted Answer

To add length to a signal trace so it matches the length of other traces in its group

Answer

Serpentine routing adds controlled length to a trace using a meander pattern to equalize its propagation delay with other traces in the same signal group.

Question 4

What is the effect of an unintended trace stub on a high-speed signal?

Accepted Answer

It creates a resonant reflection that causes a notch in the signal's frequency response

Answer

An unterminated stub behaves as a shunt transmission line that resonates at a frequency where its electrical length is a quarter wavelength, creating a notch in signal transmission.

Question 5

Why must via transitions be minimized in high-speed signal routing?

Accepted Answer

Each via introduces parasitic inductance and capacitance, causing impedance discontinuities and reflections

Answer

Every via transition adds parasitic inductance and capacitance that create impedance discontinuities, causing signal reflections and degrading high-frequency signal integrity.

(CID) Certified Interconnect Designer Practice Test

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CID CID Layout & Routing Techniques 2