CID CID Layout & Routing Techniques 2 — Questions and Answers
Question 1: What is 'daisy-chain' topology in PCB routing for buses, and what is its primary advantage?
- Connecting all loads to the source with individual traces; advantage is easy rework
- Routing a single trace that passes through each load sequentially; advantage is minimal stub lengths for source-terminated buses (Correct answer)
- Using star topology with a central hub; advantage is equal trace lengths
- Routing on alternating layers; advantage is reduced crosstalk
Correct answer: Routing a single trace that passes through each load sequentially; advantage is minimal stub lengths for source-terminated buses
Daisy-chain topology routes one continuous trace through each device in sequence, minimizing stub lengths and supporting source termination for controlled-impedance buses.
Question 2: What does 'length matching' mean for a memory bus, and to what tolerance is it typically specified?
- All traces must be exactly the same physical length within ±0.001 inch per IPC-2141 standards
- Address, data, and clock traces are matched in length within a specified tolerance (e.g., ±5 mils) to control propagation delay skew (Correct answer)
- All traces must be the same width
- Memory bus traces must match PCB edge length
Correct answer: Address, data, and clock traces are matched in length within a specified tolerance (e.g., ±5 mils) to control propagation delay skew
Length matching controls propagation delay skew across bus signals so that all bits of a data word arrive at the receiver within the timing window, with tolerances typically specified in mils by the chipset reference design.
Question 3: What is a 'serpentine' (meander) trace used for in PCB layout?
- To reduce trace impedance by increasing width
- To add length to a signal trace so it matches the length of other traces in its group (Correct answer)
- To reduce the current-carrying capacity of a trace
- To route around an obstacle while maintaining 90-degree bends
Correct answer: To add length to a signal trace so it matches the length of other traces in its group
Serpentine routing adds controlled length to a trace using a meander pattern to equalize its propagation delay with other traces in the same signal group.
Question 4: What is the effect of an unintended trace stub on a high-speed signal?
- It improves signal amplitude
- It creates a resonant reflection that causes a notch in the signal's frequency response (Correct answer)
- It reduces return loss
- It has no practical effect below 10 GHz
Correct answer: It creates a resonant reflection that causes a notch in the signal's frequency response
An unterminated stub behaves as a shunt transmission line that resonates at a frequency where its electrical length is a quarter wavelength, creating a notch in signal transmission.
Question 5: Why must via transitions be minimized in high-speed signal routing?
- Vias are expensive to fabricate and should be reduced for cost
- Each via introduces parasitic inductance and capacitance, causing impedance discontinuities and reflections (Correct answer)
- Vias reduce PCB assembly speed
- Vias add mechanical stress to the board
Correct answer: Each via introduces parasitic inductance and capacitance, causing impedance discontinuities and reflections
Every via transition adds parasitic inductance and capacitance that create impedance discontinuities, causing signal reflections and degrading high-frequency signal integrity.
Question 6: What is 'neck-down' routing and when is it necessary in PCB layout?
- Increasing trace width at component pads for thermal relief
- Temporarily reducing trace width to pass through a congested area such as a BGA escape field (Correct answer)
- Reducing trace width across the entire board to save copper
- Tapering traces near board edges for flex PCBs
Correct answer: Temporarily reducing trace width to pass through a congested area such as a BGA escape field
Neck-down routing temporarily narrows a trace to route through a congested area, such as between BGA pads, before returning to the full controlled-impedance width.
CID CID Layout & Routing Techniques 2
What is 'daisy-chain' topology in PCB routing for buses, and what is its primary advantage?