Signal Integrity & High-Speed Design Flashcards
7 cards from real CID practice questions. Tap to flip, then mark Knew It or Still Learning — missed cards come back until you master them.
Read the first 7 Signal Integrity & High-Speed Design flashcards as text
What is the 'knee frequency' of a digital signal with rise time Tr, and why is it significant?
Answer: Fknee ≈ 0.35/Tr; it approximates the highest significant spectral content of the signal
The knee frequency Fknee ≈ 0.35/Tr defines the approximate bandwidth required by a digital signal, above which additional bandwidth contributes little to waveform fidelity.
A designer wants to reduce the resonant frequency of a decoupling capacitor. Which combination of changes achieves this?
Answer: Increase capacitance and decrease ESL
The self-resonant frequency SRF = 1/(2π√(LC)); increasing C and decreasing ESL (inductance L) both lower the SRF, extending the capacitor's effective frequency range.
What physical mechanism causes 'copper roughness' to degrade signal integrity at high frequencies?
Answer: Surface roughness increases the effective path length of skin-effect current, raising conductor loss
At high frequencies where skin depth is comparable to surface roughness peaks, current must travel along a tortuous path, effectively increasing the conductor loss beyond what smooth-surface models predict.
In a controlled-impedance microstrip trace, increasing the trace width while keeping all other stackup parameters constant will:
Answer: Decrease characteristic impedance by increasing capacitance per unit length
A wider trace is closer in area to the reference plane and has greater capacitance per unit length relative to inductance, which lowers characteristic impedance Z0 = √(L/C).
Which of the following best describes the role of 'stitching vias' around a high-speed signal via?
Answer: They provide a low-inductance return current path through the reference plane transition
Stitching vias placed adjacent to a signal via provide a short, low-inductance path for return current to transition between reference planes, maintaining signal integrity through the via.
What is the 'Simultaneously Switching Output' (SSO) noise problem in PCB design?
Answer: Multiple drivers switching simultaneously cause ground bounce and power rail collapse due to shared parasitic inductance
When multiple drivers switch at the same time, their transient currents sum through the shared package and PCB inductance, creating voltage spikes on the power and ground rails.
A channel's insertion loss (IL) is measured at -6 dB at the Nyquist frequency. What does this imply about the eye opening at the receiver without equalization?
Answer: The eye amplitude will be reduced to approximately 50% of the transmitted amplitude
-6 dB corresponds to a voltage ratio of 0.5 (since 20log(0.5) = -6 dB), so the received signal amplitude at Nyquist is half the transmitted value, reducing eye opening accordingly.
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Sources & references
Exam facts on this page (fees, format, dates, passing scores) are checked against these official sources; the date is our last check. Editorial policy
- eptac.com — Test dates · verified Oct 2026
- electronics.org — Test delivery, eligibility, fees, exam format, passing score · verified Oct 2026