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CID Power Distribution & Grounding Flashcards

6 cards from real CID practice questions. Tap to flip, then mark Knew It or Still Learning — missed cards come back until you master them.

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  1. What is the primary purpose of a power distribution network (PDN) in a PCB design?

    Answer: To deliver stable voltage with minimal impedance to all active components

    A PDN is designed to supply stable, low-impedance power to all active devices across the board's operating frequency range.

  2. Which decoupling capacitor placement strategy best reduces power plane resonance in high-speed PCBs?

    Answer: Place capacitors as close to IC power pins as possible with short vias

    Decoupling capacitors placed close to IC power pins with short vias minimize parasitic inductance and most effectively suppress high-frequency noise.

  3. What phenomenon occurs when a power plane and its adjacent ground plane form a resonant cavity at certain frequencies?

    Answer: Power plane resonance

    Power plane resonance occurs when the cavity formed between power and ground planes resonates at frequencies determined by board dimensions, causing impedance spikes.

  4. In a multi-layer PCB, what is the recommended maximum distance between a power plane and its reference ground plane to minimize PDN inductance?

    Answer: 4 mils or less

    Tightly coupling the power and ground planes (4 mils or less) maximizes inter-plane capacitance and reduces PDN inductance significantly.

  5. What does the term 'target impedance' refer to in PDN design?

    Answer: The maximum allowable PDN impedance to keep voltage ripple within spec

    Target impedance is the maximum PDN impedance level calculated to keep voltage ripple within acceptable limits for the IC's power budget.

  6. Which grounding strategy is most effective for mixed-signal boards with both analog and digital circuits?

    Answer: Single unified ground plane with careful partition of analog and digital regions

    A single unified ground plane with careful physical partitioning of analog and digital regions minimizes ground impedance while preventing digital noise from coupling into analog circuits.

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Sources & references

Exam facts on this page (fees, format, dates, passing scores) are checked against these official sources; the date is our last check. Editorial policy

  1. eptac.com — Test dates · verified Oct 2026
  2. electronics.org — Test delivery, eligibility, fees, exam format, passing score · verified Oct 2026