CID Power Distribution & Grounding Flashcards

What is the self-resonant frequency (SRF) of a decoupling capacitor, and why is it important?

Answer: The frequency at which capacitive and inductive reactances cancel, making the component appear purely resistive; effective decoupling only occurs below SRF

At the SRF, a capacitor's parasitic inductance resonates with its capacitance, and above this frequency it behaves inductively, losing its decoupling effectiveness.

What does ESR stand for in the context of decoupling capacitors, and what is its effect?

Answer: Equivalent Series Resistance; it limits the minimum impedance a capacitor can achieve at resonance

ESR (Equivalent Series Resistance) is the real resistive component of a capacitor's impedance and determines the minimum impedance it can achieve at its self-resonant frequency.

Why is it recommended to use multiple capacitor values in parallel for PDN decoupling?

Answer: To cover a wider frequency range by targeting different resonance frequencies with different values

Different capacitor values have different SRFs, so using multiple values in parallel provides effective decoupling across a broader frequency spectrum.

What is the role of bulk capacitors (e.g., 10µF–100µF) in a PDN design?

Answer: Providing charge storage for low-frequency load transients and supporting the voltage regulator

Bulk capacitors handle low-frequency energy storage, supplying charge during slow load transients while the voltage regulator responds.

In PDN design, what is 'impedance flattening' and how is it achieved?

Answer: Maintaining a flat, low PDN impedance profile across the target frequency range by combining capacitor tiers

Impedance flattening means keeping PDN impedance below the target across all frequencies by strategically combining bulk, mid-range, and high-frequency decoupling capacitors.

Which via type is preferred for decoupling capacitors in high-density HDI boards to minimize parasitic inductance?

Answer: Blind or buried vias with minimal length

Blind or buried vias minimize via stub length and parasitic inductance, making them preferred for high-frequency decoupling in HDI designs.