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CID Layout & Routing Techniques Flashcards

6 cards from real CID practice questions. Tap to flip, then mark Knew It or Still Learning — missed cards come back until you master them.

Read the first 6 CID Layout & Routing Techniques flashcards as text
  1. What is 'daisy-chain' topology in PCB routing for buses, and what is its primary advantage?

    Answer: Routing a single trace that passes through each load sequentially; advantage is minimal stub lengths for source-terminated buses

    Daisy-chain topology routes one continuous trace through each device in sequence, minimizing stub lengths and supporting source termination for controlled-impedance buses.

  2. What does 'length matching' mean for a memory bus, and to what tolerance is it typically specified?

    Answer: Address, data, and clock traces are matched in length within a specified tolerance (e.g., ±5 mils) to control propagation delay skew

    Length matching controls propagation delay skew across bus signals so that all bits of a data word arrive at the receiver within the timing window, with tolerances typically specified in mils by the chipset reference design.

  3. What is a 'serpentine' (meander) trace used for in PCB layout?

    Answer: To add length to a signal trace so it matches the length of other traces in its group

    Serpentine routing adds controlled length to a trace using a meander pattern to equalize its propagation delay with other traces in the same signal group.

  4. What is the effect of an unintended trace stub on a high-speed signal?

    Answer: It creates a resonant reflection that causes a notch in the signal's frequency response

    An unterminated stub behaves as a shunt transmission line that resonates at a frequency where its electrical length is a quarter wavelength, creating a notch in signal transmission.

  5. Why must via transitions be minimized in high-speed signal routing?

    Answer: Each via introduces parasitic inductance and capacitance, causing impedance discontinuities and reflections

    Every via transition adds parasitic inductance and capacitance that create impedance discontinuities, causing signal reflections and degrading high-frequency signal integrity.

  6. What is 'neck-down' routing and when is it necessary in PCB layout?

    Answer: Temporarily reducing trace width to pass through a congested area such as a BGA escape field

    Neck-down routing temporarily narrows a trace to route through a congested area, such as between BGA pads, before returning to the full controlled-impedance width.

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Sources & references

Exam facts on this page (fees, format, dates, passing scores) are checked against these official sources; the date is our last check. Editorial policy

  1. eptac.com — Test dates · verified Oct 2026
  2. electronics.org — Test delivery, eligibility, fees, exam format, passing score · verified Oct 2026