B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 3 — Questions and Answers
Question 1: In a Harvard architecture microcontroller, which statement is correct?
- Program and data memory share the same bus
- Program and data memory use separate buses (Correct answer)
- Instructions and data occupy the same address space
- Cache is not permitted for data memory
Correct answer: Program and data memory use separate buses
Harvard architecture uses physically separate buses for instruction memory and data memory, allowing simultaneous access to both.
Question 2: The 8051 microcontroller's Program Status Word (PSW) register contains which of the following?
- Stack pointer and program counter
- Carry, auxiliary carry, overflow, and register bank select bits (Correct answer)
- Interrupt enable and priority bits
- Timer reload values for Timer 0 and Timer 1
Correct answer: Carry, auxiliary carry, overflow, and register bank select bits
The 8051 PSW holds status flags including Carry (CY), Auxiliary Carry (AC), Overflow (OV), and the RS0/RS1 register bank select bits.
Question 3: What does the term 'superscalar' mean in microprocessor design?
- The processor operates at frequencies above 1 GHz
- Multiple instructions are issued and executed simultaneously each clock cycle (Correct answer)
- The processor uses a scalar floating-point unit
- Instructions are executed in strictly sequential order
Correct answer: Multiple instructions are issued and executed simultaneously each clock cycle
A superscalar processor can issue and execute more than one instruction per clock cycle by using multiple parallel execution units.
Question 4: In DMA (Direct Memory Access) operation, the CPU relinquishes control of the bus during which phase?
- Interrupt service routine
- Bus arbitration and DMA transfer (Correct answer)
- Instruction decode stage
- Write-back stage of the pipeline
Correct answer: Bus arbitration and DMA transfer
During DMA transfer, the DMA controller requests the bus via a hold/acknowledge handshake, and the CPU tri-states its bus signals while the DMA moves data.
Question 5: Which cache write policy writes data to both the cache and main memory simultaneously on every write hit?
- Write-back
- Write-allocate
- Write-through (Correct answer)
- Copy-back
Correct answer: Write-through
Write-through policy updates main memory on every write, keeping it consistent with the cache at the cost of higher memory bandwidth.
Question 6: In ARM Thumb instruction set, instructions are encoded as:
- 64-bit fixed-length words
- 32-bit fixed-length words
- 16-bit fixed-length words (Correct answer)
- Variable-length 8-to-32-bit encodings
Correct answer: 16-bit fixed-length words
Thumb instructions use a 16-bit encoding to reduce code size, trading some flexibility compared to the full 32-bit ARM encoding.
Question 7: What is the purpose of the LOCK prefix in x86 assembly?
- Prevent other processors from accessing memory during a read-modify-write operation (Correct answer)
- Lock the instruction cache to prevent eviction
- Disable interrupts for the duration of the instruction
- Serialize all memory writes to maintain store order
Correct answer: Prevent other processors from accessing memory during a read-modify-write operation
The LOCK prefix asserts the LOCK# signal on the bus, ensuring atomic read-modify-write operations in a multiprocessor environment.
B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 3
In a Harvard architecture microcontroller, which statement is correct?