B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 2 — Questions and Answers
Question 1: In a pipelined microprocessor, a data hazard occurs when:
- An instruction depends on the result of a previous instruction not yet written back (Correct answer)
- Two instructions attempt to use the same memory address simultaneously
- The branch target address is unavailable at fetch time
- The instruction cache is full and must evict a cache line
Correct answer: An instruction depends on the result of a previous instruction not yet written back
A data hazard arises when an instruction needs a value that a prior instruction has not yet completed writing to a register.
Question 2: Which addressing mode uses the content of a register as the effective memory address?
- Immediate addressing
- Direct addressing
- Register indirect addressing (Correct answer)
- Indexed addressing
Correct answer: Register indirect addressing
Register indirect addressing uses the value stored in a specified register as the pointer to the actual memory location.
Question 3: The purpose of a Translation Lookaside Buffer (TLB) in a microprocessor is to:
- Cache frequently used virtual-to-physical address mappings (Correct answer)
- Store recently executed branch target addresses
- Buffer write operations to reduce main memory bandwidth
- Hold decoded micro-operations for out-of-order execution
Correct answer: Cache frequently used virtual-to-physical address mappings
The TLB caches recent virtual-to-physical address translations to avoid repeated page-table walks, speeding up memory accesses.
Question 4: What is the function of the barrel shifter in an ARM Cortex-M processor?
- It performs multi-bit shift or rotation in a single clock cycle (Correct answer)
- It decodes variable-length instructions
- It manages interrupt priority levels
- It converts floating-point operands to fixed-point
Correct answer: It performs multi-bit shift or rotation in a single clock cycle
The barrel shifter allows ARM to shift or rotate an operand by any number of bits in one cycle, enabling efficient multiply-by-constant operations.
Question 5: In the x86 architecture, which flag is set when the result of an unsigned arithmetic operation exceeds the maximum representable value?
- Sign Flag (SF)
- Overflow Flag (OF)
- Carry Flag (CF) (Correct answer)
- Parity Flag (PF)
Correct answer: Carry Flag (CF)
The Carry Flag (CF) indicates a carry out of the most significant bit, signaling unsigned overflow.
Question 6: Speculative execution in modern microprocessors primarily aims to:
- Reduce power consumption during idle periods
- Execute instructions along predicted paths before branches resolve (Correct answer)
- Increase cache hit rate by prefetching data
- Allow multiple threads to share functional units
Correct answer: Execute instructions along predicted paths before branches resolve
Speculative execution keeps the pipeline busy by executing instructions along the predicted branch path before knowing the actual outcome.
Question 7: Which bus cycle type does a microprocessor initiate when it needs to read an instruction from memory?
- Interrupt acknowledge cycle
- DMA cycle
- Instruction fetch cycle (Correct answer)
- I/O read cycle
Correct answer: Instruction fetch cycle
An instruction fetch cycle is a specific bus transaction where the processor reads the next instruction from the memory address indicated by the program counter.
B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 2
In a pipelined microprocessor, a data hazard occurs when: