Bachelor of Computer Engineering Microprocessor Flashcards

In a pipelined microprocessor, a data hazard occurs when:

Answer: An instruction depends on the result of a previous instruction not yet written back

A data hazard arises when an instruction needs a value that a prior instruction has not yet completed writing to a register.

Which addressing mode uses the content of a register as the effective memory address?

Answer: Register indirect addressing

Register indirect addressing uses the value stored in a specified register as the pointer to the actual memory location.

The purpose of a Translation Lookaside Buffer (TLB) in a microprocessor is to:

Answer: Cache frequently used virtual-to-physical address mappings

The TLB caches recent virtual-to-physical address translations to avoid repeated page-table walks, speeding up memory accesses.

What is the function of the barrel shifter in an ARM Cortex-M processor?

Answer: It performs multi-bit shift or rotation in a single clock cycle

The barrel shifter allows ARM to shift or rotate an operand by any number of bits in one cycle, enabling efficient multiply-by-constant operations.

In the x86 architecture, which flag is set when the result of an unsigned arithmetic operation exceeds the maximum representable value?

Answer: Carry Flag (CF)

The Carry Flag (CF) indicates a carry out of the most significant bit, signaling unsigned overflow.

Speculative execution in modern microprocessors primarily aims to:

Answer: Execute instructions along predicted paths before branches resolve

Speculative execution keeps the pipeline busy by executing instructions along the predicted branch path before knowing the actual outcome.

Which bus cycle type does a microprocessor initiate when it needs to read an instruction from memory?

Answer: Instruction fetch cycle

An instruction fetch cycle is a specific bus transaction where the processor reads the next instruction from the memory address indicated by the program counter.