CS Computer Organization & Architecture 2

Question 1

What does CPU pipelining achieve in processor design?

Accepted Answer

Overlaps the execution stages of multiple instructions to increase throughput

Answer

Pipelining divides instruction execution into stages (fetch, decode, execute, etc.) so that different instructions occupy different stages simultaneously, improving overall throughput.

Question 2

Which type of pipeline hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed?

Accepted Answer

Data hazard

Answer

A data hazard (RAW — Read After Write) occurs when a later instruction needs a value that an earlier instruction has not yet written back.

Question 3

What is the primary purpose of CPU cache memory?

Accepted Answer

To reduce average memory access latency by storing frequently used data close to the CPU

Answer

Cache exploits temporal and spatial locality to keep recently accessed data nearby, dramatically reducing the time the CPU spends waiting for main memory.

Question 4

In a multiprocessor system, what does cache coherence ensure?

Accepted Answer

All processors observe a consistent view of shared memory values

Answer

Cache coherence protocols (e.g., MESI) guarantee that if multiple caches hold copies of the same memory location, they all reflect the most recent write.

Question 5

What is a hardware interrupt?

Accepted Answer

An asynchronous signal from a device telling the CPU to stop and handle an event

Answer

Hardware interrupts are asynchronous signals from I/O devices or timers that cause the CPU to suspend its current task and execute an interrupt service routine.

(CS) Computer Science Practice Test

(CS) Computer Science Practice Test

CS Computer Organization & Architecture 2