CS Computer Organization & Architecture 2 — Questions and Answers
Question 1: What does CPU pipelining achieve in processor design?
- Overlaps the execution stages of multiple instructions to increase throughput (Correct answer)
- Increases the clock frequency by reducing pipeline depth
- Executes multiple instructions in a single clock cycle
- Reduces the number of registers needed by the CPU
Correct answer: Overlaps the execution stages of multiple instructions to increase throughput
Pipelining divides instruction execution into stages (fetch, decode, execute, etc.) so that different instructions occupy different stages simultaneously, improving overall throughput.
Question 2: Which type of pipeline hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed?
- Data hazard (Correct answer)
- Control hazard
- Structural hazard
- Memory hazard
Correct answer: Data hazard
A data hazard (RAW — Read After Write) occurs when a later instruction needs a value that an earlier instruction has not yet written back.
Question 3: What is the primary purpose of CPU cache memory?
- To reduce average memory access latency by storing frequently used data close to the CPU (Correct answer)
- To increase the total amount of addressable RAM
- To store the CPU's microcode and firmware
- To buffer I/O device data before it reaches main memory
Correct answer: To reduce average memory access latency by storing frequently used data close to the CPU
Cache exploits temporal and spatial locality to keep recently accessed data nearby, dramatically reducing the time the CPU spends waiting for main memory.
Question 4: In a multiprocessor system, what does cache coherence ensure?
- All processors observe a consistent view of shared memory values (Correct answer)
- Each processor's cache never becomes full
- Cache lines are always evicted in LRU order
- Write operations are always immediately flushed to disk
Correct answer: All processors observe a consistent view of shared memory values
Cache coherence protocols (e.g., MESI) guarantee that if multiple caches hold copies of the same memory location, they all reflect the most recent write.
Question 5: What is a hardware interrupt?
- An asynchronous signal from a device telling the CPU to stop and handle an event (Correct answer)
- A software exception caused by a division-by-zero error
- A scheduled pause inserted by the compiler for synchronization
- A CPU stall caused by a cache miss
Correct answer: An asynchronous signal from a device telling the CPU to stop and handle an event
Hardware interrupts are asynchronous signals from I/O devices or timers that cause the CPU to suspend its current task and execute an interrupt service routine.
Question 6: What distinguishes a RISC architecture from a CISC architecture?
- RISC uses a small set of simple instructions that each complete in one clock cycle (Correct answer)
- RISC supports more complex addressing modes than CISC
- CISC processors have more general-purpose registers than RISC
- RISC instructions are variable-length to improve code density
Correct answer: RISC uses a small set of simple instructions that each complete in one clock cycle
RISC (Reduced Instruction Set Computer) philosophy favors simple, uniform instructions that execute in a single cycle, enabling efficient pipelining.
Question 7: What does CPU clock speed (measured in GHz) represent?
- The number of clock cycles the CPU can execute per second (Correct answer)
- The speed at which data travels across the memory bus
- The rate at which the CPU reads from cache
- The maximum number of instructions per second the CPU can retire
Correct answer: The number of clock cycles the CPU can execute per second
Clock speed measures how many times per second the CPU's clock oscillates; each cycle can correspond to one or more pipeline stages or micro-operations.
CS Computer Organization & Architecture 2
What does CPU pipelining achieve in processor design?