CRE Design for Reliability 2 — Questions and Answers
Question 1: In a Fault Tree Analysis (FTA), which gate represents an output event occurring only if ALL input events occur simultaneously?
- OR gate
- AND gate (Correct answer)
- Inhibit gate
- Priority AND gate
Correct answer: AND gate
An AND gate in FTA produces the output event only when all of its input events occur, representing a situation where multiple failures must coincide to cause the top-level failure.
Question 2: Common Cause Failures (CCF) are particularly dangerous in redundant systems because they:
- Only affect series-connected components
- Can simultaneously defeat multiple redundant elements from a single shared cause (Correct answer)
- Are always detected by Built-In Test Equipment (BITE)
- Only occur in software-intensive systems
Correct answer: Can simultaneously defeat multiple redundant elements from a single shared cause
CCFs can simultaneously disable multiple redundant components due to a shared vulnerability (e.g., same environmental exposure, design flaw, or maintenance error), negating the benefit of redundancy.
Question 3: Highly Accelerated Life Testing (HALT) is primarily used during the design phase to:
- Certify a product meets its published MTBF specification
- Quickly find design weaknesses and operational/destruct limits by stressing beyond normal operating conditions (Correct answer)
- Validate the reliability of parts sourced from new suppliers
- Demonstrate compliance with MIL-STD-810 environmental specifications
Correct answer: Quickly find design weaknesses and operational/destruct limits by stressing beyond normal operating conditions
HALT applies stresses (thermal cycling, vibration, etc.) well beyond normal operating limits to rapidly precipitate and expose latent design weaknesses before production.
Question 4: Tolerance design (Taguchi method) in Design for Reliability focuses on making a design:
- Meet the tightest possible tolerances to eliminate all variability
- Robust and insensitive to variations in materials, manufacturing, and environment (Correct answer)
- Compliant with the minimum number of regulatory standards
- Cost-optimized by using the widest possible tolerances on all components
Correct answer: Robust and insensitive to variations in materials, manufacturing, and environment
Taguchi's robust design methodology aims to make product performance insensitive (robust) to noise factors such as manufacturing variation, component aging, and environmental conditions.
Question 5: Which reliability prediction standard is most commonly used for electronic components in US defense and aerospace applications?
- IEC 61709
- MIL-HDBK-217 (Correct answer)
- Telcordia SR-332
- FIDES Guide
Correct answer: MIL-HDBK-217
MIL-HDBK-217 is the most widely referenced US military handbook for electronic reliability prediction, providing failure rate models for a wide range of component types.
Question 6: What is the primary objective of sneak circuit analysis (SCA) in system design?
- To identify components operating above their derating levels
- To detect unintended electrical paths or conditions that can cause unwanted functions without component failure (Correct answer)
- To verify that FMEA critical items have adequate redundancy
- To simulate fault propagation through a reliability block diagram
Correct answer: To detect unintended electrical paths or conditions that can cause unwanted functions without component failure
Sneak circuit analysis identifies unexpected current paths, timing issues, or logic states in a design that can lead to unintended behavior without any component actually failing.
Question 7: During Design for Reliability, 'design margins' are established to:
- Define the cost budget allocated to reliability improvement activities
- Provide a buffer between the design's rated capability and the anticipated worst-case operating stress (Correct answer)
- Set the minimum acceptable MTBF for each subsystem
- Determine the number of prototypes required for qualification testing
Correct answer: Provide a buffer between the design's rated capability and the anticipated worst-case operating stress
Design margins ensure that even under worst-case combinations of stress, tolerance variation, and environmental conditions, the design performs within safe operating limits.
In a Fault Tree Analysis (FTA), which gate represents an output event occurring only if ALL input events occur simultaneously?