CID Design for Testability & Reliability 2

Question 1

What is the primary purpose of a boundary scan (JTAG) architecture in PCB design?

Accepted Answer

To enable in-circuit testing of board interconnects without physical test probes

Answer

Boundary scan (IEEE 1149.1/JTAG) shifts test data through cells at component pins, allowing interconnect faults to be detected without bed-of-nails probes.

Question 2

Which failure mode describes an intermittent open caused by thermal cycling stress on a solder joint?

Accepted Answer

Solder fatigue cracking

Answer

Repeated thermal expansion and contraction cycles induce mechanical fatigue in solder joints, eventually producing cracks that cause intermittent opens.

Question 3

In reliability testing, what does MTBF stand for and what does it quantify?

Accepted Answer

Mean Time Between Failures — the average operational time between successive failures in repairable systems

Answer

MTBF (Mean Time Between Failures) is the average elapsed time between inherent failures of a repairable system under normal operating conditions.

Question 4

A designer wants to verify via-to-via clearance on an inner layer without physical cross-section. Which DFT technique best supports this?

Accepted Answer

Automated X-ray inspection (AXI)

Answer

AXI uses X-ray imaging to inspect internal PCB features such as buried vias, inner-layer clearances, and hidden solder joints non-destructively.

Question 5

Which design practice improves the ability to isolate faults during in-circuit test (ICT) by preventing back-driving issues?

Accepted Answer

Inserting series resistors (typically 10–100 Ω) on signal lines

Answer

Series resistors isolate driving sources from ICT fixture drivers, preventing back-drive currents from damaging active devices during test.

(CID) Certified Interconnect Designer Practice Test

(CID) Certified Interconnect Designer Practice Test

CID Design for Testability & Reliability 2