CCP CPU Architecture & Instruction Sets 2

Question 1

Which addressing mode uses the operand value directly embedded within the instruction itself?

Accepted Answer

Immediate addressing

Answer

Immediate addressing embeds the actual data value directly in the instruction, requiring no additional memory access to fetch the operand.

Question 2

What is the primary function of the Memory Address Register (MAR)?

Accepted Answer

Holds the address of the memory location being accessed

Answer

The MAR holds the address of the memory location that the CPU wants to read from or write to during a memory access cycle.

Question 3

In a Harvard architecture, what key design choice distinguishes it from von Neumann architecture?

Accepted Answer

Instruction and data memory are physically separated

Answer

Harvard architecture uses separate memory spaces and buses for instructions and data, allowing simultaneous fetch and data access unlike the shared bus in von Neumann designs.

Question 4

What does the term 'instruction latency' refer to in CPU pipeline design?

Accepted Answer

The number of cycles required to complete an instruction before its result is available

Answer

Instruction latency is the total number of clock cycles from when an instruction begins execution until its result can be used by a subsequent instruction.

Question 5

Which CPU register typically stores the status flags such as zero, carry, and overflow?

Accepted Answer

Flags/Status Register

Answer

The Flags or Status Register (PSR/FLAGS/EFLAGS) stores condition codes set by ALU operations, used by conditional branch instructions.

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CCP CPU Architecture & Instruction Sets 2