CCP CPU Architecture & Instruction Sets 2 — Questions and Answers
Question 1: Which addressing mode uses the operand value directly embedded within the instruction itself?
- Register addressing
- Immediate addressing (Correct answer)
- Indirect addressing
- Base-relative addressing
Correct answer: Immediate addressing
Immediate addressing embeds the actual data value directly in the instruction, requiring no additional memory access to fetch the operand.
Question 2: What is the primary function of the Memory Address Register (MAR)?
- Stores the result of ALU operations
- Holds the address of the memory location being accessed (Correct answer)
- Keeps track of the next instruction to execute
- Buffers data transferred to or from memory
Correct answer: Holds the address of the memory location being accessed
The MAR holds the address of the memory location that the CPU wants to read from or write to during a memory access cycle.
Question 3: In a Harvard architecture, what key design choice distinguishes it from von Neumann architecture?
- It uses RISC instructions exclusively
- Instruction and data memory are physically separated (Correct answer)
- It has no cache hierarchy
- It uses a single shared bus for all transfers
Correct answer: Instruction and data memory are physically separated
Harvard architecture uses separate memory spaces and buses for instructions and data, allowing simultaneous fetch and data access unlike the shared bus in von Neumann designs.
Question 4: What does the term 'instruction latency' refer to in CPU pipeline design?
- The number of pipeline stages in the processor
- The number of cycles required to complete an instruction before its result is available (Correct answer)
- The maximum clock frequency of the CPU
- The size of the instruction cache
Correct answer: The number of cycles required to complete an instruction before its result is available
Instruction latency is the total number of clock cycles from when an instruction begins execution until its result can be used by a subsequent instruction.
Question 5: Which CPU register typically stores the status flags such as zero, carry, and overflow?
- Program Counter
- Stack Pointer
- Flags/Status Register (Correct answer)
- Base Register
Correct answer: Flags/Status Register
The Flags or Status Register (PSR/FLAGS/EFLAGS) stores condition codes set by ALU operations, used by conditional branch instructions.
Question 6: What is a 'superscalar' processor?
- A processor with a very high clock frequency above 4 GHz
- A processor that can issue and execute multiple instructions per clock cycle (Correct answer)
- A processor that uses VLIW instruction encoding
- A processor with more than 64 general-purpose registers
Correct answer: A processor that can issue and execute multiple instructions per clock cycle
A superscalar processor contains multiple execution units and can dispatch more than one instruction per clock cycle, achieving instruction-level parallelism.
Question 7: In x86 architecture, what is the role of the segment registers CS, DS, and SS in real mode?
- They cache recently used memory values
- They hold base addresses multiplied by 16 to form 20-bit physical addresses (Correct answer)
- They store the interrupt vector table pointers
- They define the privilege level of executing code
Correct answer: They hold base addresses multiplied by 16 to form 20-bit physical addresses
In real mode, segment registers (CS, DS, SS) are shifted left by 4 bits (multiplied by 16) and added to a 16-bit offset to produce a 20-bit physical address.
CCP CPU Architecture & Instruction Sets 2
Which addressing mode uses the operand value directly embedded within the instruction itself?