CPU Architecture & Instruction Sets Flashcards
7 cards from real CCP practice questions. Tap to flip, then mark Knew It or Still Learning — missed cards come back until you master them.
Read the first 7 CPU Architecture & Instruction Sets flashcards as text
Which addressing mode uses the operand value directly embedded within the instruction itself?
Answer: Immediate addressing
Immediate addressing embeds the actual data value directly in the instruction, requiring no additional memory access to fetch the operand.
What is the primary function of the Memory Address Register (MAR)?
Answer: Holds the address of the memory location being accessed
The MAR holds the address of the memory location that the CPU wants to read from or write to during a memory access cycle.
In a Harvard architecture, what key design choice distinguishes it from von Neumann architecture?
Answer: Instruction and data memory are physically separated
Harvard architecture uses separate memory spaces and buses for instructions and data, allowing simultaneous fetch and data access unlike the shared bus in von Neumann designs.
What does the term 'instruction latency' refer to in CPU pipeline design?
Answer: The number of cycles required to complete an instruction before its result is available
Instruction latency is the total number of clock cycles from when an instruction begins execution until its result can be used by a subsequent instruction.
Which CPU register typically stores the status flags such as zero, carry, and overflow?
Answer: Flags/Status Register
The Flags or Status Register (PSR/FLAGS/EFLAGS) stores condition codes set by ALU operations, used by conditional branch instructions.
What is a 'superscalar' processor?
Answer: A processor that can issue and execute multiple instructions per clock cycle
A superscalar processor contains multiple execution units and can dispatch more than one instruction per clock cycle, achieving instruction-level parallelism.
In x86 architecture, what is the role of the segment registers CS, DS, and SS in real mode?
Answer: They hold base addresses multiplied by 16 to form 20-bit physical addresses
In real mode, segment registers (CS, DS, SS) are shifted left by 4 bits (multiplied by 16) and added to a 16-bit offset to produce a 20-bit physical address.