BEE Digital Logic and Design 2

Question 1

Which minimization technique uses a graphical map to simplify Boolean expressions by grouping adjacent 1s?

Accepted Answer

Karnaugh map

Answer

A Karnaugh map (K-map) is a graphical tool that simplifies Boolean expressions by visually grouping adjacent cells containing 1s into power-of-2 groups.

Question 2

In a D flip-flop, what is the output Q after a rising clock edge if D = 0 and the current Q = 1?

Accepted Answer

Q becomes 0

Answer

A D flip-flop captures the value of D on the active clock edge, so Q takes the value of D (0) regardless of its previous state.

Question 3

A full adder produces a Sum and a Carry-out. What is the Carry-out when A=1, B=1, Cin=1?

Accepted Answer

1

Answer

With A=1, B=1, Cin=1, the total is 3 (binary 11), so Carry-out=1 and Sum=1.

Question 4

Which of the following represents a hazard in combinational logic circuits?

Accepted Answer

A momentary glitch in the output during input transitions

Answer

A hazard is a momentary spurious output glitch caused by unequal propagation delays along different signal paths during input transitions.

Question 5

What is the primary advantage of a synchronous counter over an asynchronous (ripple) counter?

Accepted Answer

All flip-flops are clocked simultaneously, eliminating cumulative delay

Answer

In a synchronous counter all flip-flops share the same clock, so state transitions occur simultaneously and cumulative ripple delay is eliminated.

BEE - Bachelor of Electrical Engineering Practice Test

BEE - Bachelor of Electrical Engineering Practice Test

BEE Digital Logic and Design 2