BEE Digital Circuits 2

Question 1

A JK flip-flop with J=1 and K=1 is in the SET state. After one clock pulse, what is the output?

Accepted Answer

Toggles to RESET

Answer

When J=K=1, the JK flip-flop toggles its output on each clock pulse, so it moves from SET (Q=1) to RESET (Q=0).

Question 2

Which hazard occurs in combinational circuits when a variable and its complement arrive at a gate at different times?

Accepted Answer

Static hazard

Answer

A static hazard is a momentary unwanted output transition caused by unequal propagation delays of a signal and its complement.

Question 3

What is the minimum number of NAND gates required to implement a 2-input XOR function?

Accepted Answer

4

Answer

A 2-input XOR gate can be built using 4 two-input NAND gates with the standard NAND-only XOR topology.

Question 4

In a ripple counter with 4 flip-flops, what is the maximum count before the counter resets to zero?

Accepted Answer

15

Answer

A 4-bit ripple counter counts from 0 to 2⁴−1 = 15 before rolling over to 0.

Question 5

Which logic family has the highest noise margin compared to its supply voltage?

Accepted Answer

CMOS

Answer

CMOS has noise margins of approximately 30–45% of VDD on each rail, giving it superior noise immunity relative to supply voltage.

BEE - Bachelor of Electrical Engineering Practice Test