B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 5 — Questions and Answers
Question 1: In a RISC processor, which design principle minimizes the number of clock cycles per instruction?
- Complex multi-cycle microcode for each instruction
- Single-cycle execution of simple, fixed-length instructions (Correct answer)
- Variable-length instruction encoding to maximize code density
- Dedicated hardware for each high-level language construct
Correct answer: Single-cycle execution of simple, fixed-length instructions
RISC designs use simple, fixed-length instructions that can each complete in one pipeline stage, minimizing CPI and simplifying the hardware.
Question 2: What happens to the shadow registers in a Cortex-M processor during an exception entry?
- They are cleared to zero by hardware
- Registers R0–R3, R12, LR, PC, and xPSR are automatically pushed to the stack (Correct answer)
- All 16 general-purpose registers are saved to a dedicated exception frame buffer
- Only the stack pointer is updated; other registers are left unchanged
Correct answer: Registers R0–R3, R12, LR, PC, and xPSR are automatically pushed to the stack
On Cortex-M exception entry, the hardware automatically stacks R0–R3, R12, LR, PC, and xPSR to allow an ISR written in C to run without explicit register saves.
Question 3: A microprocessor's memory-mapped I/O scheme differs from isolated (port-mapped) I/O in that:
- Memory-mapped I/O requires special IN/OUT instructions
- Isolated I/O places peripherals in the same address space as RAM
- Memory-mapped I/O uses the same address space and instructions as regular memory accesses (Correct answer)
- Memory-mapped I/O requires a dedicated I/O bus separate from the memory bus
Correct answer: Memory-mapped I/O uses the same address space and instructions as regular memory accesses
With memory-mapped I/O, peripherals occupy addresses in the main memory map and are accessed using standard load/store instructions, unlike port-mapped I/O which needs IN/OUT instructions.
Question 4: Which pipeline hazard type is caused by a conditional branch whose outcome is not known until late in the pipeline?
- Structural hazard
- Data hazard
- Control hazard (Correct answer)
- Resource hazard
Correct answer: Control hazard
Control hazards occur because the processor may fetch incorrect instructions after a branch before the actual target address is determined.
Question 5: The 8051's DPTR (Data Pointer) register is primarily used for:
- Holding the return address during subroutine calls
- Addressing external data memory and program memory via MOVX and MOVC instructions (Correct answer)
- Storing interrupt vector table addresses
- Acting as a second stack pointer for nested interrupts
Correct answer: Addressing external data memory and program memory via MOVX and MOVC instructions
The 16-bit DPTR register is used with MOVX (external RAM access) and MOVC (program memory lookup tables) instructions to address the full 64 KB external space.
Question 6: In a two-level cache hierarchy, which metric best captures the combined effect of L1 and L2 cache performance?
- L1 hit rate alone
- Average memory access time (AMAT) accounting for both levels (Correct answer)
- L2 miss penalty in clock cycles
- Total cache size in kilobytes
Correct answer: Average memory access time (AMAT) accounting for both levels
AMAT = L1 hit time + L1 miss rate × (L2 hit time + L2 miss rate × main memory penalty), capturing the contribution of both cache levels.
Question 7: What is the role of the reorder buffer (ROB) in an out-of-order microprocessor?
- It stores branch prediction history for the branch predictor
- It ensures instructions commit in program order despite out-of-order execution (Correct answer)
- It holds decoded micro-ops awaiting available functional units
- It caches TLB entries to reduce page-table walk latency
Correct answer: It ensures instructions commit in program order despite out-of-order execution
The ROB tracks all in-flight instructions and retires (commits) them in original program order, enabling precise interrupts and correct exception handling.
B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 5
In a RISC processor, which design principle minimizes the number of clock cycles per instruction?