Bachelor of Computer Engineering Microprocessor Flashcards
7 cards from real B CompE Bachelor of Computer Engineering practice questions. Tap to flip, then mark Knew It or Still Learning — missed cards come back until you master them.
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In a RISC processor, which design principle minimizes the number of clock cycles per instruction?
Answer: Single-cycle execution of simple, fixed-length instructions
RISC designs use simple, fixed-length instructions that can each complete in one pipeline stage, minimizing CPI and simplifying the hardware.
What happens to the shadow registers in a Cortex-M processor during an exception entry?
Answer: Registers R0–R3, R12, LR, PC, and xPSR are automatically pushed to the stack
On Cortex-M exception entry, the hardware automatically stacks R0–R3, R12, LR, PC, and xPSR to allow an ISR written in C to run without explicit register saves.
A microprocessor's memory-mapped I/O scheme differs from isolated (port-mapped) I/O in that:
Answer: Memory-mapped I/O uses the same address space and instructions as regular memory accesses
With memory-mapped I/O, peripherals occupy addresses in the main memory map and are accessed using standard load/store instructions, unlike port-mapped I/O which needs IN/OUT instructions.
Which pipeline hazard type is caused by a conditional branch whose outcome is not known until late in the pipeline?
Answer: Control hazard
Control hazards occur because the processor may fetch incorrect instructions after a branch before the actual target address is determined.
The 8051's DPTR (Data Pointer) register is primarily used for:
Answer: Addressing external data memory and program memory via MOVX and MOVC instructions
The 16-bit DPTR register is used with MOVX (external RAM access) and MOVC (program memory lookup tables) instructions to address the full 64 KB external space.
In a two-level cache hierarchy, which metric best captures the combined effect of L1 and L2 cache performance?
Answer: Average memory access time (AMAT) accounting for both levels
AMAT = L1 hit time + L1 miss rate × (L2 hit time + L2 miss rate × main memory penalty), capturing the contribution of both cache levels.
What is the role of the reorder buffer (ROB) in an out-of-order microprocessor?
Answer: It ensures instructions commit in program order despite out-of-order execution
The ROB tracks all in-flight instructions and retires (commits) them in original program order, enabling precise interrupts and correct exception handling.
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