B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 4 — Questions and Answers
Question 1: Which interrupt handling technique saves the program counter and status register automatically on the stack before branching to the ISR?
- Polling
- Vectored interrupt with hardware context save (Correct answer)
- Software interrupt emulation
- Daisy-chaining
Correct answer: Vectored interrupt with hardware context save
Vectored interrupts with hardware context save automatically push the return address and flags to the stack so the ISR can execute and return cleanly.
Question 2: What is the primary advantage of register windowing, as used in SPARC processors?
- Reduces branch misprediction penalty
- Speeds up procedure calls by avoiding expensive register saves to memory (Correct answer)
- Increases the number of addressable memory locations
- Allows floating-point and integer registers to share the same file
Correct answer: Speeds up procedure calls by avoiding expensive register saves to memory
Register windows provide each procedure with its own set of registers, eliminating most register spill/fill traffic to memory on function calls.
Question 3: In a 32-bit microprocessor with byte-addressable memory and 4-byte words, little-endian storage places the least significant byte at:
- The highest address of the word
- The middle address of the word
- The lowest address of the word (Correct answer)
- A fixed offset of 3 from the base address
Correct answer: The lowest address of the word
Little-endian systems store the least significant byte at the lowest (base) memory address of a multi-byte value.
Question 4: The Tomasulo algorithm in out-of-order processors uses reservation stations primarily to:
- Predict branch outcomes with high accuracy
- Eliminate WAR and WAW hazards through register renaming (Correct answer)
- Cache operand values from memory for faster access
- Schedule DMA transfers independently of the CPU pipeline
Correct answer: Eliminate WAR and WAW hazards through register renaming
Tomasulo's algorithm uses reservation stations and register renaming to eliminate write-after-read (WAR) and write-after-write (WAW) hazards, enabling out-of-order execution.
Question 5: In the context of microprocessor reset, what is the state of the program counter immediately after a cold reset on most RISC processors?
- It points to address 0x0000 always
- It is loaded from a fixed reset vector address defined by the architecture (Correct answer)
- It retains its last value before reset
- It is set to the top of the stack
Correct answer: It is loaded from a fixed reset vector address defined by the architecture
On reset, most RISC processors load the program counter from a predefined reset vector (e.g., 0xFFFFFFFC on ARM Cortex-M) specified by the architecture.
Question 6: Which technique is used to handle structural hazards caused by a single-ported memory in a pipeline?
- Forwarding (bypassing)
- Pipeline flushing
- Stalling (inserting pipeline bubbles) (Correct answer)
- Branch delay slots
Correct answer: Stalling (inserting pipeline bubbles)
A structural hazard from a single memory port is resolved by stalling the fetch stage while the memory port is occupied by a data access.
Question 7: The purpose of the prefetch queue in the Intel 8086 processor is to:
- Hold decoded instructions ready for the execution unit
- Overlap instruction fetching with instruction execution to improve throughput (Correct answer)
- Buffer operands fetched from memory before ALU processing
- Store interrupt vectors for rapid ISR dispatch
Correct answer: Overlap instruction fetching with instruction execution to improve throughput
The 8086's 6-byte prefetch queue fetches instruction bytes from memory while the execution unit processes the previous instruction, hiding memory latency.
B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 4
Which interrupt handling technique saves the program counter and status register automatically on the stack before branching to the ISR?