Bachelor of Computer Engineering Microprocessor Flashcards
7 cards from real B CompE Bachelor of Computer Engineering practice questions. Tap to flip, then mark Knew It or Still Learning — missed cards come back until you master them.
Read the first 7 Bachelor of Computer Engineering Microprocessor flashcards as text
Which interrupt handling technique saves the program counter and status register automatically on the stack before branching to the ISR?
Answer: Vectored interrupt with hardware context save
Vectored interrupts with hardware context save automatically push the return address and flags to the stack so the ISR can execute and return cleanly.
What is the primary advantage of register windowing, as used in SPARC processors?
Answer: Speeds up procedure calls by avoiding expensive register saves to memory
Register windows provide each procedure with its own set of registers, eliminating most register spill/fill traffic to memory on function calls.
In a 32-bit microprocessor with byte-addressable memory and 4-byte words, little-endian storage places the least significant byte at:
Answer: The lowest address of the word
Little-endian systems store the least significant byte at the lowest (base) memory address of a multi-byte value.
The Tomasulo algorithm in out-of-order processors uses reservation stations primarily to:
Answer: Eliminate WAR and WAW hazards through register renaming
Tomasulo's algorithm uses reservation stations and register renaming to eliminate write-after-read (WAR) and write-after-write (WAW) hazards, enabling out-of-order execution.
In the context of microprocessor reset, what is the state of the program counter immediately after a cold reset on most RISC processors?
Answer: It is loaded from a fixed reset vector address defined by the architecture
On reset, most RISC processors load the program counter from a predefined reset vector (e.g., 0xFFFFFFFC on ARM Cortex-M) specified by the architecture.
Which technique is used to handle structural hazards caused by a single-ported memory in a pipeline?
Answer: Stalling (inserting pipeline bubbles)
A structural hazard from a single memory port is resolved by stalling the fetch stage while the memory port is occupied by a data access.
The purpose of the prefetch queue in the Intel 8086 processor is to:
Answer: Overlap instruction fetching with instruction execution to improve throughput
The 8086's 6-byte prefetch queue fetches instruction bytes from memory while the execution unit processes the previous instruction, hiding memory latency.
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