B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 3

Question 1

In a Harvard architecture microcontroller, which statement is correct?

Accepted Answer

Program and data memory use separate buses

Answer

Harvard architecture uses physically separate buses for instruction memory and data memory, allowing simultaneous access to both.

Question 2

The 8051 microcontroller's Program Status Word (PSW) register contains which of the following?

Accepted Answer

Carry, auxiliary carry, overflow, and register bank select bits

Answer

The 8051 PSW holds status flags including Carry (CY), Auxiliary Carry (AC), Overflow (OV), and the RS0/RS1 register bank select bits.

Question 3

What does the term 'superscalar' mean in microprocessor design?

Accepted Answer

Multiple instructions are issued and executed simultaneously each clock cycle

Answer

A superscalar processor can issue and execute more than one instruction per clock cycle by using multiple parallel execution units.

Question 4

In DMA (Direct Memory Access) operation, the CPU relinquishes control of the bus during which phase?

Accepted Answer

Bus arbitration and DMA transfer

Answer

During DMA transfer, the DMA controller requests the bus via a hold/acknowledge handshake, and the CPU tri-states its bus signals while the DMA moves data.

Question 5

Which cache write policy writes data to both the cache and main memory simultaneously on every write hit?

Accepted Answer

Write-through

Answer

Write-through policy updates main memory on every write, keeping it consistent with the cache at the cost of higher memory bandwidth.

B CompE Bachelor of Computer Engineering Practice Test

B CompE Bachelor of Computer Engineering Practice Test

B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Microprocessor 3