B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 5

Question 1

What is the key advantage of using a Harvard architecture over a von Neumann architecture in embedded processors?

Accepted Answer

Simultaneous instruction fetch and data memory access

Answer

Harvard architecture uses separate buses for instructions and data, allowing the CPU to fetch the next instruction while reading or writing data in the same cycle.

Question 2

Speculative execution combined with a mispredicted branch requires the processor to:

Accepted Answer

Flush the pipeline and restart from the correct path

Answer

When a branch is mispredicted, any speculatively executed instructions must be squashed and the pipeline refilled from the correct target address.

Question 3

Which bus arbitration scheme guarantees that every device is eventually granted bus access, preventing starvation?

Accepted Answer

Round-robin arbitration

Answer

Round-robin arbitration cycles through all requesting devices in turn, ensuring no device is indefinitely denied access regardless of request patterns.

Question 4

In a virtual memory system with a two-level page table, how many memory accesses are needed for a TLB-miss page walk before the data access?

Accepted Answer

2

Answer

A two-level page table requires one access to the page directory and one to the page table entry before the actual data address is resolved.

Question 5

Which technique does simultaneous multithreading (SMT / Hyper-Threading) use to improve CPU utilization?

Accepted Answer

Sharing functional units among multiple hardware threads in the same cycle

Answer

SMT maintains multiple architectural states and issues instructions from several threads in the same cycle, filling otherwise idle execution slots caused by cache misses or dependencies.

B CompE Bachelor of Computer Engineering Practice Test

B CompE Bachelor of Computer Engineering Practice Test

B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 5