B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 5 — Questions and Answers
Question 1: What is the key advantage of using a Harvard architecture over a von Neumann architecture in embedded processors?
- Simultaneous instruction fetch and data memory access (Correct answer)
- Larger address space
- Simpler control unit design
- Better floating-point performance
Correct answer: Simultaneous instruction fetch and data memory access
Harvard architecture uses separate buses for instructions and data, allowing the CPU to fetch the next instruction while reading or writing data in the same cycle.
Question 2: Speculative execution combined with a mispredicted branch requires the processor to:
- Flush the pipeline and restart from the correct path (Correct answer)
- Stall all units until the branch resolves
- Write results back immediately
- Disable the branch predictor for that PC
Correct answer: Flush the pipeline and restart from the correct path
When a branch is mispredicted, any speculatively executed instructions must be squashed and the pipeline refilled from the correct target address.
Question 3: Which bus arbitration scheme guarantees that every device is eventually granted bus access, preventing starvation?
- Round-robin arbitration (Correct answer)
- Fixed-priority arbitration
- First-come-first-served without priority
- Daisy-chain arbitration
Correct answer: Round-robin arbitration
Round-robin arbitration cycles through all requesting devices in turn, ensuring no device is indefinitely denied access regardless of request patterns.
Question 4: In a virtual memory system with a two-level page table, how many memory accesses are needed for a TLB-miss page walk before the data access?
- 2 (Correct answer)
- 1
- 3
- 4
Correct answer: 2
A two-level page table requires one access to the page directory and one to the page table entry before the actual data address is resolved.
Question 5: Which technique does simultaneous multithreading (SMT / Hyper-Threading) use to improve CPU utilization?
- Sharing functional units among multiple hardware threads in the same cycle (Correct answer)
- Running separate threads on separate physical cores
- Duplicating the entire pipeline for each thread
- Using software time-slicing at the OS level
Correct answer: Sharing functional units among multiple hardware threads in the same cycle
SMT maintains multiple architectural states and issues instructions from several threads in the same cycle, filling otherwise idle execution slots caused by cache misses or dependencies.
Question 6: In a superscalar processor, a structural hazard occurs when:
- Two instructions need the same hardware resource in the same cycle (Correct answer)
- An instruction reads a register written by an earlier unfinished instruction
- A branch destination is not yet known
- An instruction is fetched from an incorrect address
Correct answer: Two instructions need the same hardware resource in the same cycle
Structural hazards arise from resource conflicts, such as two instructions simultaneously requiring a single-ported memory or a single multiply unit.
Question 7: Which cache organization minimizes conflict misses while keeping lookup hardware simpler than fully associative?
- Set-associative cache (Correct answer)
- Direct-mapped cache
- Fully associative cache
- Victim cache
Correct answer: Set-associative cache
Set-associative caches group lines into sets with a small number of ways, reducing conflict misses compared to direct-mapped while avoiding the full comparator array of fully associative caches.
B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 5
What is the key advantage of using a Harvard architecture over a von Neumann architecture in embedded processors?