B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 2

Question 1

Which cache write policy writes data to both the cache and main memory simultaneously?

Accepted Answer

Write-through

Answer

Write-through updates main memory immediately on every cache write, keeping memory consistent at the cost of higher bus traffic.

Question 2

In a 5-stage pipeline (IF, ID, EX, MEM, WB), a data hazard caused by a RAW dependency is most directly resolved by:

Accepted Answer

Adding pipeline stalls (bubbles)

Answer

Stalling the pipeline until the producing instruction writes its result eliminates read-after-write data hazards.

Question 3

Which addressing mode computes the effective address as the sum of a base register and a constant offset?

Accepted Answer

Base+offset (displacement)

Answer

Base+offset addressing adds a fixed displacement to a register value to form the memory address, commonly used for struct field access.

Question 4

Amdahl's Law states that the maximum speedup of a program is limited by:

Accepted Answer

The fraction of execution that cannot be parallelized

Answer

Amdahl's Law shows that the sequential (non-parallelizable) portion of a program caps the overall achievable speedup regardless of how many processors are added.

Question 5

What is the primary purpose of a Translation Lookaside Buffer (TLB)?

Accepted Answer

Cache recent virtual-to-physical address translations

Answer

A TLB caches page table entries so the CPU can translate virtual addresses without accessing main memory on every reference.

B CompE Bachelor of Computer Engineering Practice Test

B CompE Bachelor of Computer Engineering Practice Test

B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 2