B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 2 — Questions and Answers
Question 1: Which cache write policy writes data to both the cache and main memory simultaneously?
- Write-through (Correct answer)
- Write-back
- Write-allocate
- Write-invalidate
Correct answer: Write-through
Write-through updates main memory immediately on every cache write, keeping memory consistent at the cost of higher bus traffic.
Question 2: In a 5-stage pipeline (IF, ID, EX, MEM, WB), a data hazard caused by a RAW dependency is most directly resolved by:
- Adding pipeline stalls (bubbles) (Correct answer)
- Increasing clock frequency
- Reducing instruction count
- Using a larger cache
Correct answer: Adding pipeline stalls (bubbles)
Stalling the pipeline until the producing instruction writes its result eliminates read-after-write data hazards.
Question 3: Which addressing mode computes the effective address as the sum of a base register and a constant offset?
- Base+offset (displacement) (Correct answer)
- Immediate
- Register indirect
- Indexed
Correct answer: Base+offset (displacement)
Base+offset addressing adds a fixed displacement to a register value to form the memory address, commonly used for struct field access.
Question 4: Amdahl's Law states that the maximum speedup of a program is limited by:
- The fraction of execution that cannot be parallelized (Correct answer)
- The number of available processors
- The cache hit rate
- The memory bandwidth
Correct answer: The fraction of execution that cannot be parallelized
Amdahl's Law shows that the sequential (non-parallelizable) portion of a program caps the overall achievable speedup regardless of how many processors are added.
Question 5: What is the primary purpose of a Translation Lookaside Buffer (TLB)?
- Cache recent virtual-to-physical address translations (Correct answer)
- Store recently used data pages
- Buffer disk I/O requests
- Accelerate floating-point operations
Correct answer: Cache recent virtual-to-physical address translations
A TLB caches page table entries so the CPU can translate virtual addresses without accessing main memory on every reference.
Question 6: In MIPS R-format instructions, what does the 'shamt' field specify?
- Shift amount for shift instructions (Correct answer)
- Source register number
- Signed immediate offset
- Function code extension
Correct answer: Shift amount for shift instructions
The shamt (shift amount) field is a 5-bit value that specifies how many bit positions to shift in shift instructions.
Question 7: Which memory consistency model guarantees that all processors observe all writes in the same global order?
- Sequential consistency (Correct answer)
- Relaxed consistency
- Processor consistency
- Weak consistency
Correct answer: Sequential consistency
Sequential consistency requires that the result of execution be the same as if operations were executed in some sequential order consistent with each processor's program order.
B CompE Bachelor of Computer Engineering Bachelor of Computer Engineering Computer Architecture 2
Which cache write policy writes data to both the cache and main memory simultaneously?