Bachelor of Computer Engineering Computer Architecture Flashcards

Which cache write policy writes data to both the cache and main memory simultaneously?

Answer: Write-through

Write-through updates main memory immediately on every cache write, keeping memory consistent at the cost of higher bus traffic.

In a 5-stage pipeline (IF, ID, EX, MEM, WB), a data hazard caused by a RAW dependency is most directly resolved by:

Answer: Adding pipeline stalls (bubbles)

Stalling the pipeline until the producing instruction writes its result eliminates read-after-write data hazards.

Which addressing mode computes the effective address as the sum of a base register and a constant offset?

Answer: Base+offset (displacement)

Base+offset addressing adds a fixed displacement to a register value to form the memory address, commonly used for struct field access.

Amdahl's Law states that the maximum speedup of a program is limited by:

Answer: The fraction of execution that cannot be parallelized

Amdahl's Law shows that the sequential (non-parallelizable) portion of a program caps the overall achievable speedup regardless of how many processors are added.

What is the primary purpose of a Translation Lookaside Buffer (TLB)?

Answer: Cache recent virtual-to-physical address translations

A TLB caches page table entries so the CPU can translate virtual addresses without accessing main memory on every reference.

In MIPS R-format instructions, what does the 'shamt' field specify?

Answer: Shift amount for shift instructions

The shamt (shift amount) field is a 5-bit value that specifies how many bit positions to shift in shift instructions.

Which memory consistency model guarantees that all processors observe all writes in the same global order?

Answer: Sequential consistency

Sequential consistency requires that the result of execution be the same as if operations were executed in some sequential order consistent with each processor's program order.