PCB Signal Integrity & EMC 3

Question 1

What is crosstalk in PCB design?

Accepted Answer

Unwanted signal coupling between adjacent traces through electromagnetic fields

Answer

Interference between power and ground planes in a stackup

Answer

Signal attenuation caused by trace resistance

Answer

Timing skew between clock distribution branches

Question 2

What is Near-End Crosstalk (NEXT) and where does it appear on the victim trace?

Accepted Answer

Crosstalk appearing at the near (source) end of the victim trace, traveling backward

Answer

Crosstalk appearing at the far (load) end of the victim trace

Answer

Crosstalk induced by power supply noise

Answer

Crosstalk from a trace on an adjacent PCB layer

Question 3

What is the '3W rule' in high-speed PCB trace routing?

Accepted Answer

Center-to-center trace spacing must be at least 3 times the trace width

Answer

Trace width must be 3 times the board thickness

Answer

Trace length must not exceed 3 wavelengths

Answer

Via pad diameter must be 3 times the drill diameter

Question 4

Which layout technique most effectively reduces crosstalk between two parallel high-speed signal traces?

Accepted Answer

Inserting a ground-connected guard trace between the signal traces

Answer

Increasing the copper weight of both traces

Answer

Routing both traces on the same layer as the power plane

Answer

Using wider traces on both signals

Question 5

What is the most important placement practice for decoupling capacitors on high-frequency digital ICs?

Accepted Answer

Place capacitors as close as possible to IC power pins with minimal-length, low-inductance connections to ground

Answer

Place capacitors at the board edge for easy rework access

Answer

Use only large bulk electrolytic capacitors near the voltage regulator

Answer

Connect decoupling capacitors in series along the power rail

Question 6

Why are multiple decoupling capacitor values (e.g., 100nF and 10nF) placed in parallel on a single IC power pin?

Accepted Answer

To provide effective noise suppression across a wider frequency range since each value has a different self-resonant frequency

Answer

To increase total stored charge only

Answer

To reduce the cost of individual capacitors

Answer

To meet minimum component count requirements

Question 7

What are the two primary signal integrity concerns when routing clock signals on a high-speed PCB?

Accepted Answer

Controlling trace impedance to prevent reflections and minimizing skew between parallel clock lines

Answer

Maximizing trace length and minimizing layer changes

Answer

Using only top-layer routing and maximizing trace width

Answer

Avoiding right-angle corners and using only vertical routing