PCB Risk Assessment & Management 3 — Questions and Answers
Question 1: What risk is associated with using tin-lead (SnPb) solder on a board required to meet RoHS compliance?
- Regulatory non-compliance and potential market access restrictions (Correct answer)
- Improved thermal fatigue resistance
- Better wettability on all surfaces
- Reduced voiding in solder joints
Correct answer: Regulatory non-compliance and potential market access restrictions
RoHS restricts hazardous substances including lead; using SnPb solder violates compliance and can block product sales in regulated markets.
Question 2: During PCB fabrication, what risk does excessive copper etching (over-etching) introduce?
- Trace width reduction leading to higher resistance and potential open circuits (Correct answer)
- Stronger adhesion of copper to substrate
- Improved soldermask adhesion
- Lower dielectric constant
Correct answer: Trace width reduction leading to higher resistance and potential open circuits
Over-etching removes more copper than intended, narrowing traces, increasing resistance, and risking open circuits on fine-pitch designs.
Question 3: What failure risk is increased by placing bypass capacitors far from the IC power pins they are intended to decouple?
- Increased inductance in the decoupling path reduces high-frequency effectiveness (Correct answer)
- Lower component cost
- Improved thermal dissipation
- Better solder joint reliability
Correct answer: Increased inductance in the decoupling path reduces high-frequency effectiveness
Longer paths to bypass capacitors add parasitic inductance, reducing their ability to suppress high-frequency noise at the IC power pins.
Question 4: A designer skips Design Rule Check (DRC) before submitting a PCB for fabrication. What is the most likely risk?
- Fabrication errors such as shorts, opens, or clearance violations that could have been caught automatically (Correct answer)
- Faster time to market
- Better layer stack optimization
- Improved documentation quality
Correct answer: Fabrication errors such as shorts, opens, or clearance violations that could have been caught automatically
DRC automates the detection of design errors like clearance violations and short circuits; skipping it allows preventable defects to reach fabrication.
Question 5: What risk does a missing solder mask dam between fine-pitch SMD pads create?
- Solder bridging between adjacent pads during reflow (Correct answer)
- Improved pad adhesion strength
- Higher thermal conductivity
- Better via reliability
Correct answer: Solder bridging between adjacent pads during reflow
Without a solder mask dam, molten solder can flow between closely spaced pads, creating unintended electrical bridges.
Question 6: Which risk is specifically managed by performing a thermal simulation before PCB layout is finalized?
- Identifying hotspots that could cause component failure or board delamination before physical prototyping (Correct answer)
- Reducing layer count
- Optimizing trace routing angles
- Minimizing BOM cost
Correct answer: Identifying hotspots that could cause component failure or board delamination before physical prototyping
Thermal simulation reveals heat distribution and hotspots early, allowing design modifications before costly prototype spins.
Question 7: What is the risk of using an uncontrolled impedance stackup for a PCB carrying 10 Gbps serial data signals?
- Signal integrity degradation due to impedance mismatch causing reflections and bit errors (Correct answer)
- Higher component cost
- Increased board weight
- Reduced copper adhesion
Correct answer: Signal integrity degradation due to impedance mismatch causing reflections and bit errors
At 10 Gbps, even small impedance deviations cause significant reflections and eye diagram closure, leading to bit errors.
PCB Risk Assessment & Management 3
What risk is associated with using tin-lead (SnPb) solder on a board required to meet RoHS compliance?