PCB Risk Assessment & Management 2 — Questions and Answers
Question 1: What risk does impedance discontinuity at a via present in high-speed PCB design?
- Signal reflection and degradation at the transition point (Correct answer)
- Increased board weight
- Higher manufacturing yield
- Reduced layer count
Correct answer: Signal reflection and degradation at the transition point
Impedance discontinuities at vias cause signal reflections that degrade signal integrity, especially above 1 GHz.
Question 2: Which design practice mitigates the risk of crosstalk between adjacent signal traces on a PCB?
- Routing traces in parallel over long distances
- Maintaining a spacing of at least 3× the trace width between signals (Correct answer)
- Using wider traces for all signals
- Removing ground planes between layers
Correct answer: Maintaining a spacing of at least 3× the trace width between signals
Maintaining at least 3× trace-width spacing (3W rule) significantly reduces capacitive and inductive coupling between adjacent signals.
Question 3: A PCB will be used in a high-vibration automotive environment. Which risk should be prioritized during component selection?
- Component color coding
- Mechanical shock and vibration ratings of components and solder joints (Correct answer)
- Component brand preference
- Lead finish aesthetics
Correct answer: Mechanical shock and vibration ratings of components and solder joints
Vibration can cause solder joint fatigue and component failure, so mechanical ratings must match the application environment.
Question 4: What is the primary risk of using a single shared power plane without proper decoupling on a mixed-signal PCB?
- Excessive board thickness
- Digital switching noise coupling into sensitive analog circuitry (Correct answer)
- Reduced trace resistance
- Lower layer count requirements
Correct answer: Digital switching noise coupling into sensitive analog circuitry
Without adequate decoupling and power plane partitioning, high-frequency switching noise can propagate and corrupt analog signals.
Question 5: Which risk is introduced when controlled impedance traces are routed too close to the board edge?
- Impedance variation due to reduced dielectric boundary effects (Correct answer)
- Improved signal speed
- Lower insertion loss
- Better return path continuity
Correct answer: Impedance variation due to reduced dielectric boundary effects
The dielectric field extends beyond the trace, and proximity to the board edge alters the effective dielectric constant, shifting impedance.
Question 6: What is a primary risk of placing high-current traces near sensitive analog input traces?
- Induced voltage noise on analog inputs from magnetic field coupling (Correct answer)
- Reduced board cost
- Improved EMC performance
- Faster signal rise times
Correct answer: Induced voltage noise on analog inputs from magnetic field coupling
High-current traces generate magnetic fields that can inductively couple noise into nearby analog input lines.
Question 7: Which approach best manages the risk of electrostatic discharge (ESD) damage to sensitive ICs on a PCB?
- Removing all ground connections
- Placing TVS diodes or ESD protection devices at I/O interfaces (Correct answer)
- Using thicker copper pours
- Increasing trace width uniformly
Correct answer: Placing TVS diodes or ESD protection devices at I/O interfaces
TVS diodes and dedicated ESD protection devices clamp transient voltages before they reach sensitive IC inputs.
PCB Risk Assessment & Management 2
What risk does impedance discontinuity at a via present in high-speed PCB design?