NCA Performance Optimization & Debugging 3

Question 1

What is the primary purpose of CUDA shared memory in performance optimization?

Accepted Answer

To serve as a software-managed cache reducing repeated global memory accesses

Answer

Shared memory is on-chip SRAM that threads in a block can use to cache frequently accessed data, dramatically reducing costly global memory transactions.

Question 2

A CUDA kernel uses 64 registers per thread on an SM that supports 65,536 total registers. With 1024 threads per block, how many blocks can run concurrently per SM?

Accepted Answer

1

Answer

64 registers × 1024 threads = 65,536 registers per block, which exactly exhausts the SM's register budget, allowing only 1 block concurrently.

Question 3

In Nsight Systems, what does a gap between consecutive kernel launches in the GPU timeline most likely indicate?

Accepted Answer

CPU-side launch overhead or synchronization stall between kernels

Answer

Gaps in the GPU timeline between kernels reveal that the CPU is not keeping the GPU fed—often due to synchronization calls, data preparation, or excessive launch overhead.

Question 4

Which memory type in CUDA is best suited for read-only data broadcast to all threads in a warp simultaneously?

Accepted Answer

Constant memory

Answer

Constant memory is cached and optimized for scenarios where all threads in a warp read the same address simultaneously, providing broadcast with very low latency.

Question 5

What happens to CUDA kernel performance when thread blocks are too small (e.g., 32 threads)?

Accepted Answer

Poor occupancy limits latency hiding and underutilizes the SM

Answer

Very small blocks reduce the number of warps per block, limiting the SM's ability to hide latency through warp switching and leaving execution units idle.

(NCA) NVIDIA-Certified Associate Practice Test

(NCA) NVIDIA-Certified Associate Practice Test

NCA Performance Optimization & Debugging 3