Digital Logic and Microcomputers Flashcards

What is the primary difference between a D flip-flop and a D latch?

Answer: A flip-flop is edge-triggered; a latch is level-sensitive

A D flip-flop captures data on a clock edge, while a D latch is transparent whenever the enable signal is active (level-sensitive).

A 4-bit binary ripple counter is clocked at 16 kHz. What is the output frequency at the most significant bit (Q3)?

Answer: 1 kHz

Each flip-flop in a ripple counter divides by 2, so a 4-stage counter divides by 16: 16 kHz ÷ 16 = 1 kHz at Q3.

Which type of shift register transfers data serially in and serially out?

Answer: SISO

SISO (Serial-In, Serial-Out) receives and transmits data one bit at a time.

In a JK flip-flop, what happens when both J and K inputs are logic 1 and a clock pulse arrives?

Answer: Output toggles

With J=K=1, the JK flip-flop toggles its output on each clock pulse, solving the race condition of the SR flip-flop.

A 3-bit synchronous counter counts from 000 to 111 and repeats. How many clock pulses are needed to complete one full cycle?

Answer: 8

A 3-bit counter has 2³ = 8 unique states (000 through 111), requiring 8 clock pulses for one complete cycle.

What is the main advantage of a synchronous counter over an asynchronous (ripple) counter?

Answer: All flip-flops are clocked simultaneously, eliminating propagation delays

Synchronous counters clock all flip-flops at the same time, preventing cumulative propagation delay and glitches.

Which register operation moves all bits one position toward the most significant bit, filling the LSB with zero?

Answer: Logical left shift

A logical left shift moves all bits toward the MSB by one position and inserts a 0 at the LSB, which is equivalent to multiplying by 2.