GATE Digital Logic 3 — Questions and Answers
Question 1: What is the output of the Boolean expression F = A·(A+B)?
- A+B
- A (Correct answer)
- B
- A·B
Correct answer: A
By absorption law, A·(A+B) = A.
Question 2: A D flip-flop stores the value of D on which edge of the clock?
- High level
- Low level
- Rising edge (Correct answer)
- Both edges
Correct answer: Rising edge
A positive-edge-triggered D flip-flop captures D on the rising (positive) edge of the clock.
Question 3: How many 2-to-4 decoders (with enable) are needed to build a 4-to-16 decoder?
- 2
- 4
- 5 (Correct answer)
- 8
Correct answer: 5
One 2-to-4 decoder drives the enable of four 2-to-4 decoders, totaling 5 decoders.
Question 4: Which Karnaugh map grouping size is NOT valid when simplifying Boolean expressions?
- 1
- 2
- 3 (Correct answer)
- 4
Correct answer: 3
K-map groups must be powers of 2 (1, 2, 4, 8, …); grouping 3 cells is invalid.
Question 5: The complement of (A+B)·C using De Morgan's theorem is:
- A'·B'+C' (Correct answer)
- (A'+B')·C'
- A'·B'·C'
- (A·B)+C'
Correct answer: A'·B'+C'
Applying De Morgan's twice: [(A+B)·C]' = (A+B)' + C' = A'·B' + C'.
Question 6: In a synchronous counter, all flip-flops are clocked:
- Sequentially with delays
- By the output of the previous stage
- Simultaneously (Correct answer)
- Asynchronously
Correct answer: Simultaneously
In a synchronous counter, all flip-flops share the same clock signal and trigger simultaneously.
Question 7: Which logic family typically has the highest noise margin?
- TTL
- ECL
- CMOS (Correct answer)
- RTL
Correct answer: CMOS
CMOS has higher noise margins than TTL or ECL because its output swings nearly rail-to-rail.
GATE Digital Logic 3
What is the output of the Boolean expression F = A·(A+B)?