CS Computer Organization & Architecture 3

Question 1

What is the core concept of virtual memory?

Accepted Answer

It gives each process the illusion of a large, contiguous private address space mapped to physical RAM

Answer

It extends RAM by using CPU registers as additional storage

Answer

It compresses data in RAM to effectively double available memory

Answer

It allows multiple processes to directly share the same physical memory addresses

Question 2

What event triggers a page fault?

Accepted Answer

A process accesses a virtual memory page that is not currently loaded in physical RAM

Answer

A process writes to a read-only memory segment

Answer

A stack overflow occurs in the currently executing process

Answer

The page table becomes larger than available physical memory

Question 3

What is Direct Memory Access (DMA)?

Accepted Answer

A mechanism that lets I/O devices transfer data directly to/from memory without CPU involvement

Answer

A CPU feature allowing registers to address memory directly without a bus

Answer

A mode where the CPU bypasses cache to read directly from RAM

Answer

A technique for mapping memory-mapped I/O registers into the address space

Question 4

What is the purpose of the Translation Lookaside Buffer (TLB)?

Accepted Answer

To cache recently used virtual-to-physical address translations for faster memory access

Answer

To buffer data between the CPU and L2 cache

Answer

To translate assembly mnemonics into machine opcodes

Answer

To store the interrupt descriptor table for fast interrupt dispatch

Question 5

What does 'superscalar' execution mean in CPU design?

Accepted Answer

The CPU contains multiple execution units and can issue more than one instruction per clock cycle

Answer

The CPU runs at a clock speed higher than its rated frequency

Answer

The CPU executes instructions in a strictly sequential, in-order pipeline

Answer

The CPU uses a single wide ALU instead of multiple narrow ones

Question 6

What is the purpose of branch prediction in a pipelined CPU?

Accepted Answer

To speculatively guess the outcome of a conditional branch so the pipeline can continue without stalling

Answer

To predict how much memory a branch target will require at runtime

Answer

To preload branch instructions into a dedicated instruction cache

Answer

To identify and eliminate dead code branches at compile time

Question 7

What does 'endianness' describe in computer architecture?

Accepted Answer

The order in which bytes of a multi-byte value are stored in memory

Answer

The direction data flows across the system bus

Answer

The alignment requirement of data types in memory

Answer

The bit ordering within a single byte of data