CID Risk Assessment & Mitigation 3 — Questions and Answers
Question 1: During a design-for-manufacture (DFM) risk review, the team finds copper features within 3 mils of the board edge. What is the primary manufacturing risk?
- Copper migration causing shorts between layers
- Routing and scoring operations may expose or damage edge conductors (Correct answer)
- Increased thermal gradients during reflow soldering
- Higher probability of delamination at soldermask openings
Correct answer: Routing and scoring operations may expose or damage edge conductors
PCB routing and scoring operations require a keepout from the board edge; copper too close to the edge risks being nicked or exposed during panelization cutting.
Question 2: A CID identifies that multiple high-current power planes are separated by only 3 mils of core dielectric. What risk does this represent?
- Increased plane capacitance causing decoupling resonance
- Risk of dielectric breakdown and potential short circuit under transient overvoltage (Correct answer)
- Reduced thermal conductivity between layers
- Higher via drilling difficulty due to tight layer pitch
Correct answer: Risk of dielectric breakdown and potential short circuit under transient overvoltage
Thin dielectric between high-voltage or high-current planes reduces the voltage withstand capability, risking dielectric breakdown under transient or overvoltage conditions.
Question 3: Which risk is introduced when through-hole component leads are placed too close together in a wave solder design?
- Increased thermal resistance causing component overheating
- Solder bridging between adjacent leads during the wave solder process (Correct answer)
- Lead contamination from flux outgassing
- Reduced vibration resistance due to mechanical coupling
Correct answer: Solder bridging between adjacent leads during the wave solder process
Insufficient lead-to-lead spacing in wave soldering increases the probability of solder bridges forming between adjacent conductors.
Question 4: A design uses 0201 passive components near large through-hole connectors. What DFM risk does this combination present during reflow?
- Large connectors block UV light needed to cure the adhesive on 0201s
- Thermal shadowing from the connector may cause insufficient solder reflow on nearby 0201 pads (Correct answer)
- 0201 components will float and reposition due to solder surface tension gradients
- Connector leads will oxidize due to elevated temperatures from the small components
Correct answer: Thermal shadowing from the connector may cause insufficient solder reflow on nearby 0201 pads
Large through-hole connectors can create thermal shadows during reflow, preventing small nearby components from reaching adequate solder reflow temperatures.
Question 5: In a risk assessment of a PCB stackup, a designer notices the signal layer routing high-speed traces is not adjacent to a solid reference plane. What is the most significant risk?
- Increased via length causing stub resonance
- Uncontrolled impedance and poor return current path leading to signal integrity and EMC problems (Correct answer)
- Reduced copper pour area increasing resistive losses
- Higher likelihood of signal layer delamination under thermal stress
Correct answer: Uncontrolled impedance and poor return current path leading to signal integrity and EMC problems
Without an adjacent reference plane, the trace has uncontrolled impedance and the return current path is poorly defined, degrading both signal integrity and EMC performance.
Question 6: A CID reviews a BGA footprint and finds that the solder mask defined (SMD) pad design was used where non-solder mask defined (NSMD) is preferred. What risk does this introduce?
- SMD pads have lower thermal conductivity, risking cold solder joints
- SMD pads can reduce solder joint strength and reliability due to stress concentration at the mask edge (Correct answer)
- SMD pads increase tombstoning risk during reflow
- SMD pads reduce board thickness uniformity, affecting layer registration
Correct answer: SMD pads can reduce solder joint strength and reliability due to stress concentration at the mask edge
SMD pads concentrate mechanical stress at the solder mask edge, which can reduce solder joint reliability under thermal cycling compared to NSMD pads where the copper defines the pad size.
Question 7: During fabrication risk assessment, which stackup characteristic most affects the risk of CAF (Conductive Anodic Filament) failure?
- Use of high-Tg FR4 laminate
- Close via-to-via spacing in the presence of ionic contamination and voltage bias (Correct answer)
- Copper weight of inner plane layers
- Number of lamination pressing cycles during fabrication
Correct answer: Close via-to-via spacing in the presence of ionic contamination and voltage bias
CAF forms along glass fiber bundles between biased conductors; closely spaced vias under voltage with ionic contamination present the highest CAF risk.
CID Risk Assessment & Mitigation 3
During a design-for-manufacture (DFM) risk review, the team finds copper features within 3 mils of the board edge.
What is the primary manufacturing risk?