CID Design for Testability & Reliability 3 — Questions and Answers
Question 1: Conductive Anodic Filament (CAF) formation in a PCB is most directly associated with which design condition?
- Excessive copper weight on outer layers
- Insufficient spacing between drilled holes in high-humidity environments (Correct answer)
- High via aspect ratio combined with low resin content
- Inadequate solder mask coverage over traces
Correct answer: Insufficient spacing between drilled holes in high-humidity environments
CAF occurs when copper ions migrate along glass fiber-resin interfaces between closely spaced drilled holes under voltage bias and humidity, causing leakage or short circuits.
Question 2: What is the role of a 'test point' in PCB design for testability?
- A via used exclusively for thermal dissipation
- An accessible node allowing ICT or flying probe equipment to make electrical contact (Correct answer)
- A fiducial marker for pick-and-place alignment
- A net tie connecting two different net names
Correct answer: An accessible node allowing ICT or flying probe equipment to make electrical contact
Test points are dedicated pads or vias placed on nets to give automated test equipment reliable physical access for probing during manufacturing test.
Question 3: During accelerated life testing (ALT), Arrhenius equation is used to relate temperature to which factor?
- Signal propagation delay
- Failure rate acceleration (Correct answer)
- Dielectric constant change
- PCB warpage magnitude
Correct answer: Failure rate acceleration
The Arrhenius equation quantifies how elevated temperature accelerates chemical degradation failure mechanisms, providing an acceleration factor relative to use temperature.
Question 4: Which JTAG instruction is used to capture the logic state of all boundary scan cells from the normal circuit operation?
- BYPASS
- SAMPLE/PRELOAD (Correct answer)
- EXTEST
- IDCODE
Correct answer: SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction captures current boundary scan cell values from the functional circuit into the data register without interrupting normal operation.
Question 5: A PCB designer is minimizing electromigration risk on a high-current signal trace. What is the most effective design action?
- Increase trace length to reduce current density per unit length
- Widen the trace or add parallel traces to reduce current density (Correct answer)
- Use a thinner copper weight to improve adhesion
- Route the trace on the outer layer only
Correct answer: Widen the trace or add parallel traces to reduce current density
Electromigration risk decreases when current density is reduced by increasing conductor cross-section through wider traces or parallel routing.
Question 6: What does the term 'fault coverage' mean in the context of JTAG boundary scan testing?
- The number of JTAG-compliant ICs on the board
- The percentage of interconnect faults that boundary scan can detect given the board's BScan topology (Correct answer)
- The depth of the instruction register in each BScan device
- The clock frequency used for boundary scan operations
Correct answer: The percentage of interconnect faults that boundary scan can detect given the board's BScan topology
Fault coverage for boundary scan is the ratio of detectable interconnect faults to total possible faults, limited by the ratio of BScan-connected pins to all pins.
Question 7: Which thermal reliability parameter describes the temperature rise per unit of power dissipated from junction to ambient?
- Thermal time constant (τ)
- Junction-to-ambient thermal resistance (θJA) (Correct answer)
- Coefficient of thermal expansion (CTE)
- Derating factor
Correct answer: Junction-to-ambient thermal resistance (θJA)
θJA (theta JA) is the total thermal resistance from the semiconductor junction to the surrounding air, used to calculate junction temperature under a given power load.
CID Design for Testability & Reliability 3
Conductive Anodic Filament (CAF) formation in a PCB is most directly associated with which design condition?