CID Case Analysis & Practical Application 2 — Questions and Answers
Question 1: A high-speed PCB design operates at 10 Gbps and exhibits significant inter-symbol interference (ISI). Which practical mitigation technique should be applied first?
- Increase supply voltage
- Add pre-emphasis or de-emphasis at the transmitter (Correct answer)
- Reduce layer count
- Switch to a lower-frequency clock
Correct answer: Add pre-emphasis or de-emphasis at the transmitter
Pre-emphasis/de-emphasis boosts high-frequency components at the transmitter to counteract the channel's low-pass roll-off that causes ISI.
Question 2: During a crosstalk analysis case, you find NEXT is 8 dB higher than the design spec on a differential pair. Which change most directly reduces NEXT?
- Increase trace width
- Increase spacing between aggressor and victim pairs (Correct answer)
- Add a ground plane below layer 3
- Reduce the number of vias on the victim pair
Correct answer: Increase spacing between aggressor and victim pairs
Near-end crosstalk is primarily governed by the coupling length and spacing; increasing spacing reduces capacitive and inductive coupling.
Question 3: A case study shows a backplane connector introducing a 5 dB insertion loss spike at 7 GHz. What is the most likely root cause?
- Impedance mismatch at the connector pin stub (Correct answer)
- Excessive via anti-pad size
- Insufficient return current path
- Dielectric material variation
Correct answer: Impedance mismatch at the connector pin stub
Connector pin stubs act as resonant stubs that create notches (sharp insertion-loss spikes) at frequencies where the stub length equals a quarter wavelength.
Question 4: An engineer is reviewing a 100-ohm differential pair and finds the intra-pair skew is 12 ps over a 6-inch run. What practical step resolves this?
- Route both traces on different layers
- Add serpentine length matching within the pair (Correct answer)
- Switch to a lower-Dk dielectric
- Use wider traces to lower resistance
Correct answer: Add serpentine length matching within the pair
Intra-pair skew from length mismatch is corrected by adding serpentine tuning segments to equalize the electrical lengths of the two traces.
Question 5: A case analysis shows a PCB has significant via stub resonance degrading signal integrity at 6 GHz. Which fabrication technique eliminates via stubs?
- Controlled depth drilling (back-drilling) (Correct answer)
- Laser via formation
- Buried via routing
- Micro-via stacking
Correct answer: Controlled depth drilling (back-drilling)
Back-drilling removes the unused portion of a through-hole via stub, eliminating the stub resonance that degrades high-frequency performance.
Question 6: During return-path analysis, a high-speed signal crosses a split in the reference plane. What is the primary consequence?
- Reduced signal amplitude
- Common-mode noise and increased EMI (Correct answer)
- Increased dielectric loss
- Reduced capacitive loading
Correct answer: Common-mode noise and increased EMI
A split reference plane forces the return current to detour, creating a loop antenna that radiates common-mode noise and increases EMI.
Question 7: A practical case involves an FPGA driving a 50-ohm stripline with an output impedance of 25 ohms. What termination strategy should be applied at the load?
- Series termination at the source equal to 25 ohms
- Parallel termination of 50 ohms to ground at the receiver (Correct answer)
- AC termination using a capacitor to ground
- No termination because the FPGA drives sufficiently
Correct answer: Parallel termination of 50 ohms to ground at the receiver
Parallel termination at the load matches the line impedance and absorbs the forward wave, preventing reflections back toward the source.
CID Case Analysis & Practical Application 2
A high-speed PCB design operates at 10 Gbps and exhibits significant inter-symbol interference (ISI).
Which practical mitigation technique should be applied first?