CET Digital Electronics and Systems 2 — Questions and Answers
Question 1: Which logic family typically offers the lowest power consumption in static (non-switching) conditions?
- TTL
- ECL
- CMOS (Correct answer)
- DTL
Correct answer: CMOS
CMOS draws near-zero static current because both PMOS and NMOS transistors are never simultaneously conducting in steady state.
Question 2: A 4-bit ripple carry adder adds two 4-bit numbers. What is the maximum number of gate delays before the final sum is valid?
- 4
- 8
- 9 (Correct answer)
- 16
Correct answer: 9
Each full adder stage adds 2 gate delays for the carry, so 4 stages give 8 carry delays plus 1 final sum delay = 9 total.
Question 3: In a JK flip-flop, what state does the output enter when both J=1 and K=1 on a clock edge?
- Set
- Reset
- Toggle (Correct answer)
- No change
Correct answer: Toggle
When J=K=1, the JK flip-flop toggles its output on each active clock edge, solving the indeterminate state of the SR flip-flop.
Question 4: A 3-to-8 line decoder with active-low outputs is used to select memory chips. How many address lines does it require?
- 2
- 3 (Correct answer)
- 4
- 8
Correct answer: 3
A 3-to-8 decoder uses 3 binary address inputs to activate one of 8 output lines, enabling selection of up to 8 memory chips.
Question 5: Which Boolean expression correctly represents a 2-input XNOR gate?
- A⊕B
- AB + A'B' (Correct answer)
- A'B + AB'
- A+B
Correct answer: AB + A'B'
XNOR outputs HIGH when both inputs are equal: AB (both HIGH) or A'B' (both LOW), so the expression is AB + A'B'.
Question 6: In digital systems, what is the purpose of a tristate (three-state) buffer?
- To amplify digital signals to three voltage levels
- To allow multiple devices to share a common bus line (Correct answer)
- To convert binary to Gray code
- To add a third logic state permanently
Correct answer: To allow multiple devices to share a common bus line
Tristate buffers add a high-impedance (Hi-Z) output state so multiple devices can connect to a bus without conflict when disabled.
Question 7: A shift register has 8 bits. If data is shifted in serially at 1 MHz, how long does it take to load a complete 8-bit word?
- 1 µs
- 4 µs
- 8 µs (Correct answer)
- 16 µs
Correct answer: 8 µs
At 1 MHz clock, each bit takes 1 µs, so 8 bits require 8 clock cycles = 8 µs to fully load the register.
CET Digital Electronics and Systems 2
Which logic family typically offers the lowest power consumption in static (non-switching) conditions?