CCP CPU Architecture & Instruction Sets 5

Question 1

What is the role of the 'stack pointer' register in CPU operation?

Accepted Answer

Points to the top of the call stack, tracking the current stack frame boundary

Answer

The stack pointer (SP) register maintains the address of the top of the runtime stack, automatically updated as data is pushed onto or popped from the stack.

Question 2

In x86-64 architecture, how many general-purpose registers are available compared to the original 8086?

Accepted Answer

16 general-purpose registers (rax through r15)

Answer

x86-64 extended the original 8 general-purpose registers to 64 bits and added 8 new registers (r8–r15), giving 16 total general-purpose registers.

Question 3

What is 'cache coherency' and why is it critical in multi-core systems?

Accepted Answer

Ensuring all cores see a consistent view of shared memory despite having private caches

Answer

Cache coherency ensures that when multiple cores have cached copies of the same memory location, all cores observe a consistent and up-to-date value, preventing stale data errors.

Question 4

What does a 'context switch' involve at the CPU hardware level?

Accepted Answer

Saving and restoring the CPU register state (program counter, registers, flags) to switch between processes

Answer

A context switch saves the current process's CPU state (registers, program counter, flags) to memory and loads a previously saved state for the next process to run.

Question 5

What is the significance of the 'word size' of a CPU architecture?

Accepted Answer

It defines the natural data unit size, typically matching register width and affecting addressable memory

Answer

The word size defines the native data unit of the processor, matching general register width and typically determining the maximum directly addressable memory (e.g., 32-bit allows 4 GB addressing).

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CCP CPU Architecture & Instruction Sets 5