CCP CPU Architecture & Instruction Sets 4

Question 1

Which cache write policy writes data to both the cache and main memory simultaneously on every write?

Accepted Answer

Write-through

Answer

Write-through policy updates both the cache and main memory on every write operation, ensuring memory consistency at the cost of higher memory bus traffic.

Question 2

What is the purpose of Translation Lookaside Buffer (TLB) in a CPU?

Accepted Answer

To cache virtual-to-physical address translations, speeding up memory access

Answer

The TLB is a small hardware cache of recent virtual-to-physical address translations, reducing the overhead of walking the page table on every memory access.

Question 3

In a pipelined CPU, what causes a 'structural hazard'?

Accepted Answer

Two instructions requiring the same hardware resource at the same time

Answer

A structural hazard occurs when two or more instructions need the same physical hardware resource (like a single memory port or ALU) simultaneously, preventing their concurrent execution.

Question 4

What distinguishes a 'reduced instruction set' (RISC) approach in terms of instruction execution time?

Accepted Answer

Most instructions are designed to execute in a single clock cycle

Answer

RISC designs target single-cycle execution for most instructions by using simple, uniform instruction formats and load/store memory access patterns, enabling efficient pipelining.

Question 5

What is 'speculative execution' in modern CPU design?

Accepted Answer

Executing instructions before it is certain they will be needed, based on predictions

Answer

Speculative execution allows the CPU to execute instructions ahead of confirmed need (e.g., after a predicted branch), discarding results if the speculation proves incorrect.

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CCP CPU Architecture & Instruction Sets 4