CCP CPU Architecture & Instruction Sets 3 — Questions and Answers
Question 1: What is 'branch prediction' and why is it used in modern CPUs?
- A technique to reduce cache misses by prefetching data
- A method to speculatively fetch and execute instructions along the predicted path of a branch (Correct answer)
- A way to compress instruction encodings in memory
- A hardware mechanism to detect pipeline hazards
Correct answer: A method to speculatively fetch and execute instructions along the predicted path of a branch
Branch prediction allows the CPU to speculatively continue fetching and executing instructions along the most likely branch path, avoiding pipeline stalls while waiting for the branch outcome.
Question 2: Which type of hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed?
- Structural hazard
- Control hazard
- Data hazard (Correct answer)
- Cache hazard
Correct answer: Data hazard
A data hazard (Read-After-Write or RAW dependency) occurs when an instruction needs the output of a preceding instruction that is still in the pipeline.
Question 3: What does 'out-of-order execution' allow a CPU to do?
- Execute instructions from multiple threads simultaneously
- Execute instructions in an order different from program order to avoid stalls (Correct answer)
- Reorder memory writes for cache coherency
- Skip instructions that are predicted not to execute
Correct answer: Execute instructions in an order different from program order to avoid stalls
Out-of-order execution lets the CPU dynamically reorder instructions so that independent instructions execute while dependent ones wait, maximizing throughput.
Question 4: In CISC architectures, what is the significance of microcode?
- It is a form of firmware stored in ROM that translates complex instructions into simpler micro-operations (Correct answer)
- It refers to the smallest possible cache line size
- It is a compressed form of machine code used in embedded systems
- It describes the bit-width of the internal data bus
Correct answer: It is a form of firmware stored in ROM that translates complex instructions into simpler micro-operations
Microcode is a layer of hardware-level instructions stored in ROM within the CPU that breaks down complex CISC instructions into sequences of simpler internal micro-operations for execution.
Question 5: What is the purpose of register renaming in modern processors?
- To increase the number of addressable registers in the ISA
- To eliminate false data dependencies (WAW and WAR hazards) by mapping ISA registers to a larger physical register file (Correct answer)
- To rename variables in compiled code for better cache utilization
- To assign registers to threads in a multithreaded processor
Correct answer: To eliminate false data dependencies (WAW and WAR hazards) by mapping ISA registers to a larger physical register file
Register renaming maps architectural registers to a larger set of physical registers, eliminating write-after-write (WAW) and write-after-read (WAR) hazards that would otherwise stall the pipeline.
Question 6: What is the difference between SIMD and MIMD parallel processing models?
- SIMD applies one instruction to multiple data streams; MIMD applies multiple independent instructions to multiple data streams (Correct answer)
- SIMD uses multiple processors; MIMD uses a single processor with vector units
- SIMD is used only in GPUs; MIMD is used only in CPUs
- SIMD requires shared memory; MIMD requires distributed memory
Correct answer: SIMD applies one instruction to multiple data streams; MIMD applies multiple independent instructions to multiple data streams
SIMD (Single Instruction, Multiple Data) applies one instruction to many data elements simultaneously, while MIMD (Multiple Instruction, Multiple Data) allows independent instruction streams on independent data.
Question 7: What does the 'fetch-decode-execute' cycle describe?
- The three-layer memory hierarchy of L1, L2, and L3 caches
- The fundamental sequence of steps a CPU performs to process each instruction (Correct answer)
- The stages of a context switch between processes
- The pipeline stages used exclusively in RISC processors
Correct answer: The fundamental sequence of steps a CPU performs to process each instruction
The fetch-decode-execute cycle is the basic operational loop of a CPU: fetch the instruction from memory, decode its opcode and operands, then execute the specified operation.
CCP CPU Architecture & Instruction Sets 3
What is 'branch prediction' and why is it used in modern CPUs?