CPU Architecture & Instruction Sets Flashcards
7 cards from real CCP practice questions. Tap to flip, then mark Knew It or Still Learning — missed cards come back until you master them.
Read the first 7 CPU Architecture & Instruction Sets flashcards as text
What is 'branch prediction' and why is it used in modern CPUs?
Answer: A method to speculatively fetch and execute instructions along the predicted path of a branch
Branch prediction allows the CPU to speculatively continue fetching and executing instructions along the most likely branch path, avoiding pipeline stalls while waiting for the branch outcome.
Which type of hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed?
Answer: Data hazard
A data hazard (Read-After-Write or RAW dependency) occurs when an instruction needs the output of a preceding instruction that is still in the pipeline.
What does 'out-of-order execution' allow a CPU to do?
Answer: Execute instructions in an order different from program order to avoid stalls
Out-of-order execution lets the CPU dynamically reorder instructions so that independent instructions execute while dependent ones wait, maximizing throughput.
In CISC architectures, what is the significance of microcode?
Answer: It is a form of firmware stored in ROM that translates complex instructions into simpler micro-operations
Microcode is a layer of hardware-level instructions stored in ROM within the CPU that breaks down complex CISC instructions into sequences of simpler internal micro-operations for execution.
What is the purpose of register renaming in modern processors?
Answer: To eliminate false data dependencies (WAW and WAR hazards) by mapping ISA registers to a larger physical register file
Register renaming maps architectural registers to a larger set of physical registers, eliminating write-after-write (WAW) and write-after-read (WAR) hazards that would otherwise stall the pipeline.
What is the difference between SIMD and MIMD parallel processing models?
Answer: SIMD applies one instruction to multiple data streams; MIMD applies multiple independent instructions to multiple data streams
SIMD (Single Instruction, Multiple Data) applies one instruction to many data elements simultaneously, while MIMD (Multiple Instruction, Multiple Data) allows independent instruction streams on independent data.
What does the 'fetch-decode-execute' cycle describe?
Answer: The fundamental sequence of steps a CPU performs to process each instruction
The fetch-decode-execute cycle is the basic operational loop of a CPU: fetch the instruction from memory, decode its opcode and operands, then execute the specified operation.